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root/cvsroot/CMSSW/PhysicsTools/PythonAnalysis/test/test.py
Revision: 1.1
Committed: Wed Oct 7 13:30:30 2009 UTC (15 years, 6 months ago) by decosa
Content type: text/x-python
Branch: MAIN
CVS Tags: CMSSW_6_2_0, CMSSW_6_2_0_pre7_TS133806, CMSSW_5_3_11_patch3, CMSSW_6_1_2_SLHC6_patch1, CMSSW_5_3_11_patch2, CMSSW_5_3_11_patch1, CMSSW_6_2_0_pre8, CMSSW_6_1_2_SLHC6, CMSSW_4_1_8_patch13, CMSSW_6_1_2_SLHC5, CMSSW_5_3_11, CMSSW_6_2_0_pre7_TS132947, CMSSW_4_4_5_patch3, CMSSW_6_2_0_pre7_g496p02, CMSSW_6_2_0_pre7, CMSSW_5_3_10_patch2, CMSSW_6_1_2_SLHC4_patch1, CMSSW_6_1_2_SLHC4, CMSSW_6_1_2_SLHC2_patch3, CMSSW_6_2_0_pre6_patch1, CMSSW_6_1_2_SLHC2_patch2, CMSSW_6_2_0_pre6, CMSSW_5_3_10_patch1, CMSSW_6_1_2_SLHC3, CMSSW_6_1_2_SLHC2_patch1, CMSSW_4_1_8_patch11, CMSSW_5_3_10, CMSSW_6_1_2_SLHC2, CMSSW_6_2_0_pre5slc6, CMSSW_5_3_9_patch3, CMSSW_6_1_2_SLHC1, CMSSW_6_2_0_pre5, CMSSW_6_1_X_2012-12-19-0200, CMSSW_6_0_X_2012-08-07-0200, CMSSW_5_2_X_2012-05-03-0200, CMSSW_5_2_X_2012-03-08-0200, CMSSW_5_0_X_2011-12-18-0200, CMSSW_4_4_X_2011-06-09-0400, CMSSW_5_3_9_patch2, CMSSW_6_1_2, CMSSW_6_2_0_pre4, CMSSW_5_3_9_patch1, CMSSW_6_2_0_pre3, CMSSW_6_1_1_SLHCphase2tk1, CMSSW_5_3_9, CMSSW_6_1_1_SLHCphase1tk1, CMSSW_5_2_9, CMSSW_6_2_0_pre2, CMSSW_6_1_1, CMSSW_5_3_8_patch3, CMSSW_5_3_7_patch6, CMSSW_6_2_0_pre1, CMSSW_5_3_8_patch2, CMSSW_5_3_8_patch1, CMSSW_5_3_8, CMSSW_5_3_8_HI_patch2, CMSSW_5_3_7_patch5, CMSSW_5_3_8_HI_patch1, CMSSW_5_2_6_patch2, CMSSW_6_1_0, CMSSW_5_3_8_HI, CMSSW_5_3_7_patch4, CMSSW_5_3_7_patch3, CMSSW_6_0_1_PostLS1v2_patch4, CMSSW_6_1_0_pre8, CMSSW_5_3_7_25nspatch1, CMSSW_5_3_7_patch2, CMSSW_6_1_0_pre7_TS127013, CMSSW_6_0_1_PostLS1v2_patch3, CMSSW_6_1_0_pre7, CMSSW_5_3_7_patch1, CMSSW_6_1_0_pre6_TS126203_TS126341_patch1, CMSSW_5_3_7_alcapatch1, CMSSW_6_1_0_pre6g496cand01, CMSSW_5_3_7, CMSSW_6_0_1_PostLS1v2_patch2, CMSSW_6_0_1_PostLS1v2_patch1, CMSSW_6_1_0_pre6_TS126203_TS126341, CMSSW_6_1_0_pre6, CMSSW_6_0_1_PostLS1v2, CMSSW_4_4_5_patch2, CMSSW_5_3_6_patch1, CMSSW_5_2_8, CMSSW_6_1_0_pre5, CMSSW_6_0_1_PostLS1v1, CMSSW_5_2_7_hltpatch2, CMSSW_5_3_4_TC125616patch1, CMSSW_6_0_1, CMSSW_5_3_4_patch2, CMSSW_6_1_0_pre3_TS124729, CMSSW_6_1_0_pre4, CMSSW_5_3_5, CMSSW_5_3_3_patch3, CMSSW_5_3_4_patch1, CMSSW_6_1_0_pre3, CMSSW_4_4_5_patch1, CMSSW_5_2_7, CMSSW_5_3_4, CMSSW_5_3_2_patch5, CMSSW_6_1_0_pre2, CMSSW_5_3_4_cand2, CMSSW_5_3_4_cand1_patch1, CMSSW_6_0_0_patch1, CMSSW_6_0_0_SLHCtkpre1, CMSSW_6_1_0_pre1, CMSSW_5_3_4_cand1, CMSSW_6_0_0_TS123272, CMSSW_5_2_6_patch1, CMSSW_6_0_0, CMSSW_4_4_5, CMSSW_5_3_3_patch2, CMSSW_4_2_8_SLHChcal6, CMSSW_5_3_3, CMSSW_5_3_3_patch1, CMSSW_6_0_0_pre11, CMSSW_6_0_0_pre10, CMSSW_4_2_8_SLHChcal5, CMSSW_6_0_0_pre9, CMSSW_4_2_8_SLHCstd2_patch2, CMSSW_4_2_8_SLHCtk3_patch2, CMSSW_4_2_8_SLHChcal2_patch3, CMSSW_5_3_2_patch4, CMSSW_6_0_0_pre8, CMSSW_4_2_8_SLHCstd2_patch1, CMSSW_4_2_8_SLHCtk3_patch1, CMSSW_4_2_8_SLHChcal4_patch4, CMSSW_5_3_3_cand1, CMSSW_5_3_2_patch2, CMSSW_5_3_2_metpatch1, CMSSW_5_2_6_hltpatch1, CMSSW_4_2_8_SLHChcal4_patch3, CMSSW_6_0_0_pre7py273, CMSSW_5_2_6, CMSSW_5_3_2_patch1, CMSSW_4_2_8_SLHChcal4_patch2, CMSSW_4_2_8_SLHChcal4_patch1, CMSSW_5_3_2, CMSSW_6_0_0_pre7, CMSSW_5_2_4_hltpatch4, CMSSW_6_0_0_pre6g495p01, CMSSW_5_2_5_patch3, CMSSW_5_2_5_patch2, CMSSW_6_0_0_pre6, CMSSW_5_3_1, CMSSW_4_1_8_patch10, CMSSW_5_2_5_ecalpatch1, CMSSW_6_0_0_pre5, CMSSW_5_3_0_patch1, CMSSW_4_2_8_SLHChcal4, CMSSW_4_2_8_SLHCtk3, CMSSW_5_2_5, CMSSW_5_2_5_patch1, CMSSW_4_2_9_HLT1_bphpatch4, CMSSW_sm120515a, CMSSW_4_2_8_SLHCstd2, CMSSW_5_3_0, CMSSW_6_0_0_pre4, CMSSW_5_2_4_hltpatch2, CMSSW_4_2_9_HLT1_bphpatch3, CMSSW_6_0_X, CMSSW_5_2_5_cand1, CMSSW_4_2_8_SLHC2_patch2, CMSSW_4_2_8_SLHCtk_patch2, CMSSW_4_2_8_SLHChcal2_patch2, CMSSW_5_2_4_patch4, CMSSW_6_0_0_pre3, CMSSW_5_2_4_patch3, CMSSW_4_2_8_SLHCtk2, CMSSW_5_2_4_patch2, CMSSW_4_2_8_SLHChcal3, CMSSW_4_2_8_SLHCstd, CMSSW_5_2_4_patch1, CMSSW_5_2_4, CMSSW_5_2_3_patch4, CMSSW_4_2_8_SLHC2_patch1, CMSSW_4_2_8_SLHCtk_patch1, CMSSW_4_2_8_SLHChcal2_patch1, CMSSW_4_2_9_HLT1_bphpatch2, CMSSW_5_2_3_patch3, CMSSW_4_2_9_HLT1_bphpatch1, CMSSW_6_0_0_pre2, CMSSW_5_2_3_patch2, CMSSW_5_2_3_patch1, CMSSW_5_2_3, CMSSW_6_0_0_pre1, CMSSW_5_1_3, CMSSW_5_2_2, CMSSW_5_2_1, CMSSW_4_4_4, CMSSW_5_1_2_patch1, CMSSW_5_2_0, CMSSW_5_1_1_patch3, CMSSW_5_2_0_pre5_TS117504, CMSSW_5_1_2, CMSSW_5_2_0_pre6, CMSSW_5_1_1_patch2, CMSSW_4_4_3_patch1, CMSSW_5_1_1_patch1, CMSSW_5_2_0_pre5, CMSSW_5_1_1, CMSSW_5_0_1_patch3, CMSSW_4_1_8_patch8, CMSSW_5_0_1_patch2, CMSSW_5_2_0_pre4, CMSSW_4_2_8_SLHCtk, CMSSW_5_0_1_patch1, CMSSW_5_2_0_pre3HLT, CMSSW_4_2_8_p7rootfix, CMSSW_5_2_0_pre3, CMSSW_5_0_1, CMSSW_5_2_0_pre2_TS113282, CMSSW_4_4_3, CMSSW_5_0_0_patch1, CMSSW_5_2_0_pre2, CMSSW_5_2_0_pre1, CMSSW_5_1_0_pre2, CMSSW_5_1_0_pre1, CMSSW_4_1_8_patch7, CMSSW_4_4_2_patch10, CMSSW_5_0_0, CMSSW_4_2_8_SLHChcal, CMSSW_4_4_2_patch9, CMSSW_4_4_2_patch8, CMSSW_4_1_8_patch6, CMSSW_5_0_0_pre7, CMSSW_4_2_8_SLHC1, CMSSW_4_2_8_SLHC2, CMSSW_5_0_0_pre6g494, CMSSW_4_4_2_patch7, CMSSW_4_1_8_patch5, CMSSW_5_0_0_pre6, CMSSW_4_4_2_patch6, CMSSW_4_1_8_patch4, CMSSW_5_0_0_pre5_root532rc1, CMSSW_4_4_2_patch5, CMSSW_4_4_2_patch4, CMSSW_4_4_2_patch3, CMSSW_4_2_3_SLHC4_patch1, CMSSW_4_4_2_patch2, CMSSW_5_0_0_pre5, CMSSW_4_4_2_patch1, V00-05-04, CMSSW_4_4_2, CMSSW_5_0_0_pre4, CMSSW_4_4_0_patch4, CMSSW_4_2_8_patch7, CMSSW_5_0_0_pre3, CMSSW_4_4_1, CMSSW_5_0_0_pre2, CMSSW_4_4_0_patch3, CMSSW_4_2_8_patch6, CMSSW_4_4_0_patch2, CMSSW_4_2_9_HLT2_hltpatch1, CMSSW_4_2_9_HLT1_hltpatch2, CMSSW_4_4_0_patch1, CMSSW_4_2_8_patch5, CMSSW_4_2_9_HLT3, CMSSW_5_0_0_pre1, CMSSW_4_4_0, CMSSW_4_2_9_HLT2, CMSSW_4_2_8_patch4, CMSSW_4_2_9_HLT1_patch1, CMSSW_4_4_0_pre10, CMSSW_4_1_8_patch1, CMSSW_4_2_8_patch3, CMSSW_4_4_0_pre9, CMSSW_4_1_8, V00-05-03, CMSSW_4_2_8_patch2, CMSSW_4_2_9_HLT1, CMSSW_4_2_9_HLT, CMSSW_4_4_0_pre8, CMSSW_4_2_7_hltpatch3, CMSSW_4_1_7_patch3, CMSSW_4_2_8_patch1, CMSSW_4_4_0_pre7_g494p02, CMSSW_4_1_7_patch2, CMSSW_4_4_0_pre7, CMSSW_4_4_0_pre6, CMSSW_4_2_8, CMSSW_4_2_7_hltpatch2, CMSSW_4_2_3_SLHC4, CMSSW_4_2_3_SLHC2, CMSSW_4_2_7_hltpatch1, CMSSW_4_2_5_hltpatch1, CMSSW_4_2_7_patch2, CMSSW_4_4_0_pre5, CMSSW_4_2_7_patch1, CMSSW_4_2_7, CMSSW_4_1_7_patch1, CMSSW_4_4_0_pre4, CMSSW_4_3_0_dqmpatch2, CMSSW_4_2_6, CMSSW_4_4_0_pre3, CMSSW_4_3_0_dqmpatch1, CMSSW_4_3_0, CMSSW_4_4_0_pre2, CMSSW_4_2_4_patch2, CMSSW_4_2_4_hltpatch1, CMSSW_4_2_5, CMSSW_4_1_7, logger_cbern_19Jun11-09h37m04s, CMSSW_4_4_0_pre1, CMSSW_4_3_0_pre6_dqmIO, CMSSW_4_3_0_pre7, CMSSW_4_2_4_patch1, CMSSW_4_2_3_SLHC3, CMSSW_4_2_4, CMSSW_4_1_6_patch1, CMSSW_4_2_3_patch5, CMSSW_4_2_3_patch4, CMSSW_4_3_0_pre6, CMSSW_4_2_3_patch3, V00-05-02, CMSSW_4_2_3_patch2, CMSSW_4_3_0_pre5, CMSSW_4_2_3_patch1, CMSSW_4_2_3_SLHC_pre1, CMSSW_4_1_6, CMSSW_4_2_2_patch2, CMSSW_4_2_3, CMSSW_4_2_2_patch1, CMSSW_4_3_0_pre4, CMSSW_4_2_1_patch2, CMSSW_4_2_2_SLHC_pre1, CMSSW_4_1_4_patch4, CMSSW_4_2_2, CMSSW_4_1_5, CMSSW_4_1_4_patch3, CMSSW_4_2_1_patch1, CMSSW_4_3_0_pre3, CMSSW_4_2_1, CMSSW_4_1_4_patch2, CMSSW_4_1_4_patch1, CMSSW_4_1_4, CMSSW_4_2_0, CMSSW_4_3_0_pre2, CMSSW_4_3_0_pre1, CMSSW_4_1_3_patch2, CMSSW_4_2_0_pre8, CMSSW_4_1_3, CMSSW_4_1_2, CMSSW_4_1_2_patch1, CMSSW_3_11_3, CMSSW_4_2_0_pre7, CMSSW_3_11_2, CMSSW_4_2_0_pre6, CMSSW_3_11_1_hltpatch1, CMSSW_3_11_1_hclpatch1, CMSSW_3_11_1_patch3, CMSSW_3_9_9_patch1, CMSSW_3_9_9, CMSSW_4_2_0_pre5, CMSSW_4_2_0_pre4, CMSSW_3_11_1_patch1, CMSSW_4_2_0_pre3, CMSSW_3_11_1, CMSSW_3_9_8_patch2, CMSSW_4_2_0_pre2, CMSSW_3_9_8_patch1, CMSSW_3_9_8, CMSSW_4_2_0_pre1, CMSSW_3_11_0, CMSSW_3_10_1, CMSSW_3_11_0_pre4, CMSSW_3_11_0_pre5, CMSSW_3_11_0_pre3, CMSSW_3_11_0_pre2, CMSSW_3_9_7, CMSSW_3_10_0, CMSSW_3_9_6, CMSSW_3_8_7_patch1, CMSSW_3_11_0_pre1, CMSSW_3_10_0_pre9, CMSSW_3_9_5_patch2, CMSSW_3_10_0_pre8, CMSSW_3_10_0_pre7g494c1, CMSSW_3_9_5_patch1, CMSSW_3_10_0_pre7, CMSSW_3_8_7, CMSSW_3_9_5, CMSSW_3_10_0_pre6, CMSSW_3_9_4, CMSSW_3_10_0_pre5, CMSSW_3_9_3, CMSSW_3_9_2_patch5, CMSSW_3_10_0_pre4, CMSSW_3_9_2_patch4, CMSSW_3_9_2_patch3, CMSSW_3_9_2_patch2, CMSSW_3_9_2_patch1, CMSSW_3_9_2, CMSSW_3_10_0_pre3, CMSSW_3_9_1_patch1, CMSSW_3_9_1, CMSSW_3_10_0_pre2, CMSSW_3_10_0_pre1, CMSSW_3_9_0, V00-05-01, CMSSW_3_9_0_pre7, CMSSW_3_9_0_pre6, V00-05-00, CMSSW_3_9_0_pre5, CMSSW_3_9_0_pre4, CMSSW_3_9_0_pre3, CMSSW_3_9_0_pre2, CMSSW_3_9_0_pre1, V00-04-00, HEAD
Log Message:
Provenance handling code - unit test. Version to test

File Contents

# Content
1 from readProv import *
2 from diffProv import *
3 import unittest
4
5
6 if __name__=="__main__":
7
8 class testEdmProvDiff(unittest.TestCase):
9
10 def setUp(self):
11 self._r=filereader()
12 self._d=difference(str(2))
13
14 def testStartswith(self):
15 """ Check the method startswith() of class filereader
16 """
17 r='Module: modulename'
18 a=self._r.startswith(r)
19 self.assertEqual(a, True)
20 s='ESSource: modulename'
21 b=self._r.startswith(s)
22 self.assertEqual(b, True)
23 t='ESModule: modulename'
24 c=self._r.startswith(t)
25 self.assertEqual(c, False)
26 u='SModule: modulename'
27 d=self._r.startswith(u)
28 self.assertEqual(d, False)
29
30
31 def testKeys(self):
32 """ Check modules names stored by the method readfile()
33 of class filereader
34 """
35 moduleblock1={}
36 moduleblock2={}
37 moduleblock1=self._r.readfile('newfile')
38 moduleblock2=self._r.readfile('newfile2')
39 keys1=moduleblock1.keys()
40 keys1.sort()
41 keys2=moduleblock2.keys()
42 keys2.sort()
43 self.assertEqual(keys1,['HLT2','Processing'])
44 self.assertEqual(keys2,['HLT','Processing'])
45
46 def testValueModule(self):
47 """ Check modules stored by the method readfile()
48 of class filereader
49 """
50 moduleblock={}
51 file='newfile'
52 moduleblock=self._r.readfile(file)
53 key='HLT2'
54 try:
55 moduleblock[key]
56 except KeyError:
57 print "No process "+key + "run "
58 try:
59 label=moduleblock[key][0][0]
60 except ValueError:
61 print "No module "+label +" in the process "+ key + ' in the file '+ file
62
63 value=moduleblock[key][0][1]
64 block=('Module: genCandidatesForMET HLT2', ' parameters: {', ' excludeResonances: bool tracked = false', ' partonicFinalState: bool tracked = false','}{', '}{', '}', '')
65
66 self.assertEqual(block,value)
67
68 def testListDifferences(self):
69 """ Check the differences between the parameters of a same module
70 run on two different edm files with different parameter values
71 """
72 moduleblock1={}
73 moduleblock2={}
74 moduleblock1=self._r.readfile('newfile')
75 moduleblock2=self._r.readfile('newfile2')
76 key1='HLT2'
77 key2='HLT'
78 module1=moduleblock1[key1][0][1]
79 module2=moduleblock2[key2][0][1]
80 file1= 'first file'
81 file2= 'second file'
82 result=['excludeResonances: bool tracked = false [first file]',' true [second file]', 'partonicFinalState: bool tracked = false [first file]',' true [second file]']
83 self.assertEqual(result, self._d.list_diff(module1,module2,file1,file2))
84
85
86
87 unittest.main()