TIBTIDNotes/TIBTIDIntNote/SiStripComponents.tex

\section{The TIB/TID Components}
\label{sec:Components}

\subsection{The Silicon Module}

The TIB and TID module consist of a carbon fiber support
frame that holds a single silicon
sensor~\cite{ref:mask}\cite{ref:sensors} and the front-end electronics
hybrid circuit. The sensor is aligned with respect to the same frame 
aluminum insets that are used to fix the module the ledges in such a
way the sensor positioning is guaranteed with respect to the support
structure.\\

The double-sided TIB layers and TID rings are equipped with module
sandwiches capable of a space point measurement and obtained by
coupling back-to-back a $r\phi$ module and a special ``stereo''
module with the sensor tilted by $100\mrad$.

%The stereo module just
%differ from the $r\phi$ one in the details needed to cope with the
%different sensor orientation.

{\bf FIX ME: descrizione/tabella dei vari tipi di moduli.}

%The readout chip
%pitch (44$\mu$m) is matched to the sensor pitch via an aluminum deposited glass substrate
%fanout circuit (pitch
%adapter). The hybrid circuit, which houses the front-end chips and ancillary
%electronics, is realized using kapton multilayer technology integrating the power and 
%signal cables. \\

A single sided module of the TID ring 1 module shown in 
Fig.~\ref{fig:moduletid}. A TIB double-sided module is shown in Fig.~\ref{fig:moduleds}

%\begin{figure}[!htb]
%\begin{center}
%  \includegraphics[width=0.60\textwidth]{Figs/moduless.pdf}
%\end{center}
%\caption{A 4 chips TIB single sided module mounted on its transportation carrier.}
%\label{fig:moduless}       % Give a unique label
%\end{figure}

\begin{figure}[!htb]
\begin{center}
  \includegraphics[width=0.3\textwidth, height=0.45\textwidth,angle=90]{Figs/module-R1.pdf}
\hskip 5mm
  \includegraphics[height=0.3\textwidth, width=0.45\textwidth]{Figs/moduleds.pdf}
\end{center}
\caption{A ring 1 TID module (left panel). A TIB double-sided module,
  the ``stereo'' module is visible reflected by a mirror (rigth panel).}
\label{fig:moduleds}       % Give a unique label
\label{fig:moduletid}      
\end{figure}

%\subsection{The Front-end Electronics}
The multilayer kapton hybrid circuit holds the near front-end
electronics consisting of four main components: the readout chips,
APV25 and three ASICs (the Multiplexer, the PLL and the DCU). All
devices are addressed and controlled by a I$^2$C serial bus.\\
The signals coming from each strip are processed by four or six front-end readout chips
(APV25), connected to the silicon sensor strips by means of a glass
substrate pitch-adapter. The APV25~\cite{ref:apv}
is a 128 channel chip built in radiation hard 0.25 $\mu$m 
CMOS technology~\cite{ref:radtol}. Each channel consists of a
preamplifier coupled to a CR-RC 50ns shaper. The shaper output is sampled at 40MHz into 
a 192 cells pipeline that allows trigger latencies up to 4$\mu$s.\\
The APV25 can operate in {\it peak mode} or in {\it deconvolution
  mode}. In the former the shaping time is $50\ns$; in the latter, by
  using a deconvolution filter~\cite{ref:deconvolution}, the 
  effective shaping time is 25ns. In addition, there is also the
  possibility to switch on (Inv) or off an inverter to fully exploit
  the dynamic range of the preamplifier with signals of both
  polarity. Standard operation mode for Silicon Sensor is with
  inverter on.  
{\bf FIX ME: ma serve??? Nel seguito non si fa mai menzione dei vari
  modi di funzionamento dell'APV - forse da aggiungere nela
  descrizione del ped-noi run?}

On receiving a level 1 trigger the APV25 sends out serially
%, at 20MHz rate, 
the 128 analogue signals together with information about the
pipeline address and the chip error status; two APV25 are multiplexed
on a differential line by the Multiplexer chip~\cite{ref:mux}. 
In absence of data to stream out, for synchronization purposes, the
APV issues a 25ns pulse called ``tick mark''
with a period of 70 clock cycles.\\
The PLL chip\cite{ref:pll} allows the clock to be delayed to
compensate for path differences of control signals and for any
electronics delay. The PLL also decodes the trigger signals that are
encoded on the clock line.\\
The Detector Control Unit (DCU) contains an eight-channel ADC,
two constant current sources and a temperature sensor. It
monitors two sets of thermistors, one on the sensor
and one on the hybrid, its own internal temperature, the
silicon sensor bias current and the two (1.25 V and
2.5 V) low voltages. Each DCU has a unique hardware identification 
number (called \textit{DCU Hardware ID}) that can also be read through
the $I^2C$ interface. By means of this number each module has an
unique identification.

\subsection{The Analog Opto Hybrid}

The Analog-Opto Hybrids~\cite{ref:aoh} (AOH) performs the
electrical-to-optical conversion of the electrical signals of the two
or three APV25 pairs, depending on the module type, by means of
radiation hard lasers~\cite{Gill:2005ui}. There is one AOH 
per module, sitting on a ledge glued on the cooling pipe very close to
the silicon module hybrid. Multi-mode optical fiber~\cite{ref:opto}
transport the signal to the FEDs~\cite{ref:fed} for the
digitization. Each AOH has two or three two meter long pig-tail
optical fibres ending with an optical plug.\\
The electrical signals arrive to the AOH through hybrid 
kapton cable. The AOH is powered by the same cable.
By means of the AOH control logic the laser working parameters GAIN
and BIAS can be set via $I^2C$  control registers.
The GAIN parameter can be used to compensate the loss of signal
on the optical link to the FED input. The GAIN parameter has four
possible values, 0, 1, 2, 3, corresponding to a nominal
gain value of 0.5, 0.75, 1, 1.25, respectively, normalized at
GAIN=3. During normal operation, if no damage was done to the line and
ideal connections, it is normally set to 1. 
The BIAS parameter regulates the current threshold for the laser
diodes and can be set in the range 0$\div$127. The optimal value
strongly depends on temperature and also on irradiation.

\subsection{The Control Ring}
\label{fig:ctrlring} 

The control of the modules front-end electronic is implemented by means of a
hierarchical structure organized in groups of modules~\cite{ref:dohm}. Each group is 
controlled by a Communication and Control Unit (CCU) taht represents a
``node'' in a ``token-ring'' formed by several daisy-chained CCUs and
known as {\it control ring}. The control ring is mastered by a Front End
Controller, FEC~\cite{ref:opto}, located outside the experiment by
means of optical signals. The entire TIB and TID contains roughly 100
Control Rings.

\begin{description}
\item[Digital Opto Hybrid Module] The FEC optical signals are converted into electrical signals by two DOHs 
(Digital Opto-Hybrid) that send clock, trigger, and control signals to
the token ring of CCUs. The DOHs are physically located on a board,
Digital Opto Hybrid Module~\cite{ref:dohm} (DOHM), that provides up to
15 ports (7 on the main DOHM board plus 8 on its
secondary extension or AUX) to implement the token ring. Each port
connects the DOHM to a CCU located on the Mother Cable head
via a 26 poles flat cable. 
To cope with possible CCU failures that would affect the entire ring, the
control ring features the so called {\it redundancy} by means of
a clever layout, shown in Fig.~\ref{fig:redundancy}, that exploits the
two input/output replicas of the CCUs: each CCU is connected to the
two nearby CCUs through the primary circuit (``A'') and to the second
next CCUs through the secondary circuit (``B'') by which a failing CCU
can be bypassed. To cope with the failure either of the last
CCU or of the primary DOH (A), the DOHM holds a ``dummy CCU'' and a
spare DOH (B).
\begin{figure}
\begin{center}
  \includegraphics[width=0.85\textwidth]{Figs/default_redundancy.pdf}
\end{center}
\caption{Scheme of primary and secondary circuit of the ring. }
\label{fig:redundancy}
\end{figure}
If no CCU is connected to a given DOHM port, a special loop-back plug
must be  inserted in order to ensure the continuity of the primary
and secondary control circuits. 
%The redundancy properties of the system 
%are preserved by observing two ``rules'', i.e. a) if an even number of plugs is needed,
%plugs must be organized in  pairs, each pair having the two plugs inserted in consecutive ports, b) 
%if  an odd number of plugs is needed, one plug must be placed in the last DOHM port 
%(before the dummy CCU), and the remaining ones following the previous rule.
\item[CCU] The CCU serves a group of modules and performs the following tasks:
distributes the clock/trigger and the hard reset to the modules;
dispatches the instructions received from the 
FEC to the modules APV25s and the other ASICS via $I^2C$ or
vice-versa, i.e. addresses the readings from the $I^2C$ devices to the FEC.
Each CCU device sits on a CCU-Module (or CCUM) which carries also
buffering chips and a DCU. Each CCU has an hardware address
configurable by means of appropriate solder pads on the CCUM board to
be shorted or not by a SMD pull up resistor. 
%either directed to themselves or to the devices connected to them. The first case is used
%for example to read the Status Register of the CCU or to raise its output PIA reset lines.
%While in the latter case
%commands are translated to the $I^2C$ protocol and forwarded to the 
%other devices located on the sensor modules or AOH; in case of
%a reply from the $I^2C$ device, the reverse process is done by the CCU, which addresses the
%information to the FEC.
\end{description}

\subsection{The Mother Cable}
The  electrical connections between a group of modules served by the
same CCU are done by the {\it Mother Cable}~\cite{ref:mc}, a flexible
multi-layer kapton copper circuit. An example is shown in
Fig.~\ref{fig:fotomc}. The mother cable is mounted on the carbon fiber
support structure underneath the modules. 
The mother cable holds a CCUM and distributes the $I^2C$ serial data (SDA)
and clock (SCL) lines, the hard reset (PIA reset) line and the
clock/trigger to each module.
The mother cable is connected to a Power Supply unit via two sockets
located at the edge and feeds the modules with low voltages (1.25~V,
2.5~V) and the high voltage.

In the TIB the mother cable coincides
with the string, i.e. six modules
(three double sides assemblies) in L1 and L2 and three modules in L3
and L4. In the TID each mother cable serves a 90-degrees sector,
i.e. six modules (three double-sided assemblies) in R1 and R2 and
five modules in R3.

\begin{figure}
\begin{center}
  \includegraphics[width=0.85\textwidth]{Figs/mothercable.pdf}
\end{center}
\caption{A mother cable mounted on a shell. In the two upper boxes, the detail of the CCU
installed on MC and the connectors at the edge of the MC.}
\label{fig:fotomc}
\end{figure}

Revision:	1.4
Committed:	Mon Mar 9 15:41:05 2009 UTC (16 years, 1 month ago) by sguazz
Content type:	application/x-tex
Branch:	MAIN
Changes since 1.3:	+185 -327 lines
Log Message:	Text revision, some figures added, some removed
#	User	Rev	Content
1	lino	1.2	\section{The TIB/TID Components}
2	sguazz	1.1	\label{sec:Components}
3	lino	1.2
4	sguazz	1.4	\subsection{The Silicon Module}
5	lino	1.2
6	sguazz	1.4	The TIB and TID module consist of a carbon fiber support
7			frame that holds a single silicon
8			sensor~\cite{ref:mask}\cite{ref:sensors} and the front-end electronics
9			hybrid circuit. The sensor is aligned with respect to the same frame
10			aluminum insets that are used to fix the module the ledges in such a
11			way the sensor positioning is guaranteed with respect to the support
12			structure.\\
13
14			The double-sided TIB layers and TID rings are equipped with module
15			sandwiches capable of a space point measurement and obtained by
16			coupling back-to-back a $r\phi$ module and a special ``stereo''
17			module with the sensor tilted by $100\mrad$.
18
19			%The stereo module just
20			%differ from the $r\phi$ one in the details needed to cope with the
21			%different sensor orientation.
22
23			{\bf FIX ME: descrizione/tabella dei vari tipi di moduli.}
24
25			%The readout chip
26			%pitch (44$\mu$m) is matched to the sensor pitch via an aluminum deposited glass substrate
27			%fanout circuit (pitch
28			%adapter). The hybrid circuit, which houses the front-end chips and ancillary
29			%electronics, is realized using kapton multilayer technology integrating the power and
30			%signal cables. \\
31
32			A single sided module of the TID ring 1 module shown in
33			Fig.~\ref{fig:moduletid}. A TIB double-sided module is shown in Fig.~\ref{fig:moduleds}
34
35			%\begin{figure}[!htb]
36			%\begin{center}
37			% \includegraphics[width=0.60\textwidth]{Figs/moduless.pdf}
38			%\end{center}
39			%\caption{A 4 chips TIB single sided module mounted on its transportation carrier.}
40			%\label{fig:moduless} % Give a unique label
41	lino	1.2	%\end{figure}
42
43	sguazz	1.1	\begin{figure}[!htb]
44			\begin{center}
45	sguazz	1.4	\includegraphics[width=0.3\textwidth, height=0.45\textwidth,angle=90]{Figs/module-R1.pdf}
46			\hskip 5mm
47			\includegraphics[height=0.3\textwidth, width=0.45\textwidth]{Figs/moduleds.pdf}
48	sguazz	1.1	\end{center}
49	sguazz	1.4	\caption{A ring 1 TID module (left panel). A TIB double-sided module,
50			the ``stereo'' module is visible reflected by a mirror (rigth panel).}
51	sguazz	1.1	\label{fig:moduleds} % Give a unique label
52	lino	1.2	\label{fig:moduletid}
53			\end{figure}
54
55	lino	1.3	%\subsection{The Front-end Electronics}
56	sguazz	1.4	The multilayer kapton hybrid circuit holds the near front-end
57			electronics consisting of four main components: the readout chips,
58			APV25 and three ASICs (the Multiplexer, the PLL and the DCU). All
59			devices are addressed and controlled by a I$^2$C serial bus.\\
60			The signals coming from each strip are processed by four or six front-end readout chips
61			(APV25), connected to the silicon sensor strips by means of a glass
62			substrate pitch-adapter. The APV25~\cite{ref:apv}
63	sguazz	1.1	is a 128 channel chip built in radiation hard 0.25 $\mu$m
64	sguazz	1.4	CMOS technology~\cite{ref:radtol}. Each channel consists of a
65			preamplifier coupled to a CR-RC 50ns shaper. The shaper output is sampled at 40MHz into
66			a 192 cells pipeline that allows trigger latencies up to 4$\mu$s.\\
67			The APV25 can operate in {\it peak mode} or in {\it deconvolution
68			mode}. In the former the shaping time is $50\ns$; in the latter, by
69			using a deconvolution filter~\cite{ref:deconvolution}, the
70			effective shaping time is 25ns. In addition, there is also the
71			possibility to switch on (Inv) or off an inverter to fully exploit
72			the dynamic range of the preamplifier with signals of both
73			polarity. Standard operation mode for Silicon Sensor is with
74			inverter on.
75			{\bf FIX ME: ma serve??? Nel seguito non si fa mai menzione dei vari
76			modi di funzionamento dell'APV - forse da aggiungere nela
77			descrizione del ped-noi run?}
78
79			On receiving a level 1 trigger the APV25 sends out serially
80			%, at 20MHz rate,
81			the 128 analogue signals together with information about the
82			pipeline address and the chip error status; two APV25 are multiplexed
83			on a differential line by the Multiplexer chip~\cite{ref:mux}.
84			In absence of data to stream out, for synchronization purposes, the
85			APV issues a 25ns pulse called ``tick mark''
86			with a period of 70 clock cycles.\\
87			The PLL chip\cite{ref:pll} allows the clock to be delayed to
88			compensate for path differences of control signals and for any
89			electronics delay. The PLL also decodes the trigger signals that are
90			encoded on the clock line.\\
91			The Detector Control Unit (DCU) contains an eight-channel ADC,
92	sguazz	1.1	two constant current sources and a temperature sensor. It
93			monitors two sets of thermistors, one on the sensor
94			and one on the hybrid, its own internal temperature, the
95	lino	1.3	silicon sensor bias current and the two (1.25 V and
96	sguazz	1.4	2.5 V) low voltages. Each DCU has a unique hardware identification
97			number (called \textit{DCU Hardware ID}) that can also be read through
98			the $I^2C$ interface. By means of this number each module has an
99			unique identification.
100
101			\subsection{The Analog Opto Hybrid}
102
103			The Analog-Opto Hybrids~\cite{ref:aoh} (AOH) performs the
104			electrical-to-optical conversion of the electrical signals of the two
105			or three APV25 pairs, depending on the module type, by means of
106			radiation hard lasers~\cite{Gill:2005ui}. There is one AOH
107			per module, sitting on a ledge glued on the cooling pipe very close to
108			the silicon module hybrid. Multi-mode optical fiber~\cite{ref:opto}
109			transport the signal to the FEDs~\cite{ref:fed} for the
110			digitization. Each AOH has two or three two meter long pig-tail
111			optical fibres ending with an optical plug.\\
112			The electrical signals arrive to the AOH through hybrid
113			kapton cable. The AOH is powered by the same cable.
114			By means of the AOH control logic the laser working parameters GAIN
115			and BIAS can be set via $I^2C$ control registers.
116			The GAIN parameter can be used to compensate the loss of signal
117			on the optical link to the FED input. The GAIN parameter has four
118			possible values, 0, 1, 2, 3, corresponding to a nominal
119			gain value of 0.5, 0.75, 1, 1.25, respectively, normalized at
120			GAIN=3. During normal operation, if no damage was done to the line and
121			ideal connections, it is normally set to 1.
122			The BIAS parameter regulates the current threshold for the laser
123			diodes and can be set in the range 0$\div$127. The optimal value
124			strongly depends on temperature and also on irradiation.
125	lino	1.2
126	sguazz	1.4	\subsection{The Control Ring}
127	sguazz	1.1	\label{fig:ctrlring}
128	lino	1.3
129	sguazz	1.4	The control of the modules front-end electronic is implemented by means of a
130			hierarchical structure organized in groups of modules~\cite{ref:dohm}. Each group is
131			controlled by a Communication and Control Unit (CCU) taht represents a
132			``node'' in a ``token-ring'' formed by several daisy-chained CCUs and
133			known as {\it control ring}. The control ring is mastered by a Front End
134			Controller, FEC~\cite{ref:opto}, located outside the experiment by
135			means of optical signals. The entire TIB and TID contains roughly 100
136			Control Rings.
137
138			\begin{description}
139			\item[Digital Opto Hybrid Module] The FEC optical signals are converted into electrical signals by two DOHs
140			(Digital Opto-Hybrid) that send clock, trigger, and control signals to
141			the token ring of CCUs. The DOHs are physically located on a board,
142			Digital Opto Hybrid Module~\cite{ref:dohm} (DOHM), that provides up to
143			15 ports (7 on the main DOHM board plus 8 on its
144	sguazz	1.1	secondary extension or AUX) to implement the token ring. Each port
145	sguazz	1.4	connects the DOHM to a CCU located on the Mother Cable head
146			via a 26 poles flat cable.
147			To cope with possible CCU failures that would affect the entire ring, the
148			control ring features the so called {\it redundancy} by means of
149			a clever layout, shown in Fig.~\ref{fig:redundancy}, that exploits the
150			two input/output replicas of the CCUs: each CCU is connected to the
151			two nearby CCUs through the primary circuit (``A'') and to the second
152			next CCUs through the secondary circuit (``B'') by which a failing CCU
153			can be bypassed. To cope with the failure either of the last
154			CCU or of the primary DOH (A), the DOHM holds a ``dummy CCU'' and a
155			spare DOH (B).
156	sguazz	1.1	\begin{figure}
157			\begin{center}
158			\includegraphics[width=0.85\textwidth]{Figs/default_redundancy.pdf}
159			\end{center}
160			\caption{Scheme of primary and secondary circuit of the ring. }
161			\label{fig:redundancy}
162			\end{figure}
163	sguazz	1.4	If no CCU is connected to a given DOHM port, a special loop-back plug
164			must be inserted in order to ensure the continuity of the primary
165			and secondary control circuits.
166			%The redundancy properties of the system
167			%are preserved by observing two ``rules'', i.e. a) if an even number of plugs is needed,
168			%plugs must be organized in pairs, each pair having the two plugs inserted in consecutive ports, b)
169			%if an odd number of plugs is needed, one plug must be placed in the last DOHM port
170			%(before the dummy CCU), and the remaining ones following the previous rule.
171			\item[CCU] The CCU serves a group of modules and performs the following tasks:
172			distributes the clock/trigger and the hard reset to the modules;
173			dispatches the instructions received from the
174			FEC to the modules APV25s and the other ASICS via $I^2C$ or
175			vice-versa, i.e. addresses the readings from the $I^2C$ devices to the FEC.
176			Each CCU device sits on a CCU-Module (or CCUM) which carries also
177			buffering chips and a DCU. Each CCU has an hardware address
178			configurable by means of appropriate solder pads on the CCUM board to
179			be shorted or not by a SMD pull up resistor.
180			%either directed to themselves or to the devices connected to them. The first case is used
181			%for example to read the Status Register of the CCU or to raise its output PIA reset lines.
182			%While in the latter case
183			%commands are translated to the $I^2C$ protocol and forwarded to the
184			%other devices located on the sensor modules or AOH; in case of
185			%a reply from the $I^2C$ device, the reverse process is done by the CCU, which addresses the
186			%information to the FEC.
187			\end{description}
188
189			\subsection{The Mother Cable}
190			The electrical connections between a group of modules served by the
191			same CCU are done by the {\it Mother Cable}~\cite{ref:mc}, a flexible
192			multi-layer kapton copper circuit. An example is shown in
193			Fig.~\ref{fig:fotomc}. The mother cable is mounted on the carbon fiber
194			support structure underneath the modules.
195			The mother cable holds a CCUM and distributes the $I^2C$ serial data (SDA)
196			and clock (SCL) lines, the hard reset (PIA reset) line and the
197			clock/trigger to each module.
198			The mother cable is connected to a Power Supply unit via two sockets
199			located at the edge and feeds the modules with low voltages (1.25~V,
200			2.5~V) and the high voltage.
201
202			In the TIB the mother cable coincides
203			with the string, i.e. six modules
204			(three double sides assemblies) in L1 and L2 and three modules in L3
205			and L4. In the TID each mother cable serves a 90-degrees sector,
206			i.e. six modules (three double-sided assemblies) in R1 and R2 and
207			five modules in R3.
208	sguazz	1.1
209	sguazz	1.4	\begin{figure}
210			\begin{center}
211			\includegraphics[width=0.85\textwidth]{Figs/mothercable.pdf}
212			\end{center}
213			\caption{A mother cable mounted on a shell. In the two upper boxes, the detail of the CCU
214			installed on MC and the connectors at the edge of the MC.}
215			\label{fig:fotomc}
216			\end{figure}
217	sguazz	1.1