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1		\section{The TIB/TID Components}
2		\label{sec:Components}
3	–	Full views of a finished half of the TIB and a TID Disk are shown in Fig.~\ref{fig:tibtid}.
4	–
5	–	This section describes the main TIB and TID components: detailed description will be made for items which are
6	–	of particular importance for the integration activities, both for assemblies and tests.
7	–
8	–	\begin{figure}[!htb]
9	–	\begin{center}
10	–	\includegraphics[height=0.5\textwidth]{Figs/TIB-assembled.pdf}
11	–	\includegraphics[width=0.5\textwidth, angle=90]{Figs/TID-disk.pdf}
12	–	\end{center}
13	–	\caption{Half of TIB assembled and one TID disk on the left and on the right respectively.  The 4 shells
14	–	structure is visible for the TIB; the 3 rings structure is visible for the Disk.}
15	–	\label{fig:tibtid}       % Give a unique label
16	–	\end{figure}
17	–
18	–	Table~\ref{table:layers} summarize the number of the different components for the several layers/rings
19	–	of the TIB/TID.
20	–
21	–	\begin{table}[!htb]
22	–	\begin{center}
23	–	\begin{tabular}{|l||c|c|c|c|c|c|c|}
24	–	\hline
25	–	Layer & \# mechanical & \# cooling  &  DS/SS & \# of modules  & \# of channels & \# Control & \# Mother  \\
26	–	&   structures  &  circuits    &  layer &  total         & per module         &  Rings     &  Cables  \\
27	–	\hline
28	–	\hline
29	–	TIB L1  & 4 shells &    & DS & & & &  \\
30	–	TIB L2  & 4 shells &    & DS & & & &  \\
31	–	TIB L3  & 4 shells &    & SS & & & &  \\
32	–	TIB L4  & 4 shells &    & SS & & & &  \\
33	–	TID R1  & 6 rings  & 24 & DS & 288 & 768 & 12 & 48 \\
34	–	TID R2  & 6 rings  & 24 & DS & 288 & 768 & 12 & 48 \\
35	–	TID R3  & 6 rings  & 24 & SS & 240 & 512 & 12 & 48 \\
36	–	\hline
37	–	\end{tabular}
38	–	\caption[smallcaption]{ Details on the different layers/rings of the TIB/TID. }
39	–	\label{table:layers}
40	–	\end{center}
41	–	\end{table}
42	–
43	–
44	–	\subsection{Mechanical Structures}
45	–
46	–	The TIB support structure was designed structured as 4 concentric layers
47	–	and realized using mainly carbon fiber. Each of these layers
48	–	is made up of four half-cylinder (called "shells")
49	–	being split vertically at $z=0$ and horizontally at $y=0$.
50	–	Each shell hosts services both on its external and its internal surface.
51	–	Modules and associated services, that are on the same side of a shell and at the same $\phi$ coordinate
52	–	constitute a  \textit{string}.
53	–	%A TIB shell is shown on Fig.~\ref{fig:tibshell}).
54	–
55	–	%Each cooling loop hosts three modules placed in a straight row, which is called a
56	–	%A string of modules is connected to the same CCU, thus forming a control branch.
57	–
58	–	%\begin{figure}
59	–	%\centering
60	–	%\includegraphics[width=\textwidth]{   }
61	–	%\caption{TIB shell: are visible the internal and external parts, the cooling pipes and the string}
62	–	%\label{fig:tibshell}
63	–	%\end{figure}
64	–
65	–	The 6 TID disks are all identical and each one is  made out of three rings. Each ring consists of
66	–	a support mechanical structure made of an annular carbon fiber honeycomb, hosting modules and services on both sides to decrease the density  and therefore providing a better accessibility during ring integration and  disk assembly.
67	–
68	–	Each TID+ and TID- is obtained by inserting, positioning and fixing each disk into a carbon fiber cylinder called {\it Service Cylinder}. Each Service Cylinder has several holes at the position of disk, in order to allow the connection of the power lines and to route out all the fibers of the disk. The service Cylinder is also  used to connect mechanically TIB+/- and TID+/-,
69	–	and to route out the services of the TIB and of the TID.
70	–
71	–	%\begin{figure}
72	–	%\centering
73	–	%\includegraphics[width=\textwidth]{   }
74	–	%\caption{TID ring }
75	–	%\label{fig:tidring}
76	–	%\end{figure}
77	–
78	–
79	–	The cooling in the TIB/TID is distributed via aluminum circuits called cooling pipes
80	–	that  are bent into loops and soldered to inlet/outlet manifolds near a large flange.
81	–	The thermal connection between pipes and sensor modules is made with Aluminum ledges which are
82	–	precisely glued on the carbon fiber support structure and in good thermal contact with the pipes.
83	–	On each ledge there are two threaded M1 holes onto which the modules are tightened.
84	–	Precisely drilled slots, coaxial with the threaded holes, are the reference point where
85	–	insets are stick in providing mechanical reference for modules. An example for a TIB module
86	–	is shown in Fig.~\ref{fig:module_cooling}).
87	–
88	–
89	–	\begin{figure}
90	–	\centering
91	–	\includegraphics[width=\textwidth]{Figs/module_cooling.pdf}
92	–	\caption{Module Cooling .
93	–	\textbf{Upper picture:} a whole cooling loop with six ledges to hold three modules and three
94	–	smaller ledges to hold Analog Opto-Hybrids (two more cooling loops are partially visible).
95	–	\textbf{Lower picture:} a detail of a cooling loop. The cooling fluid direction
96	–	is evidenced with blue arrows, and the precision insets for module insertion are circled in
97	–	red. A module mounted on the nearby position is also visible.}
98	–	\label{fig:module_cooling}
99	–	\end{figure}
100	–
3
4		\subsection{The Silicon Module}
103	–	The silicon module design has been kept as simple as possible to ease their
104	–	mass production and integration. In TIB and TID the module hosts a single silicon sensor~\cite{ref:mask}\cite{ref:sensors}  glued on a carbon fiber support
105	–	frame which also holds the front-end electronics hybrid. The sensor is aligned  with respect to the same  frame aluminum insets that are used to mount the module on the shell:  this choice guarantee the best reproducibility
106	–	of the sensor position in the global shell coordinate system.\\
107	–	The readout chip
108	–	pitch (44$\mu$m) is matched to the sensor pitch via an aluminum deposited glass substrate
109	–	fanout circuit (pitch
110	–	adapter). The hybrid circuit, which houses the front-end chips and ancillary
111	–	electronics, is realized using kapton multilayer technology integrating the power and
112	–	signal cables. \\
113	–	Fig~\ref{fig:moduless} and \ref{fig:moduleds} show a TIB single and double-sided module
114	–	respectively. Fig.~\ref{fig:moduletid} show a R1 TID module.
115	–
116	–	{\it Commento LD: Dobbiamo aggiungere delle foto di tutte le geometrie ?
117	–	}
5
6	+	The TIB and TID module consist of a carbon fiber support
7	+	frame that holds a single silicon
8	+	sensor~\cite{ref:mask}\cite{ref:sensors} and the front-end electronics
9	+	hybrid circuit. The sensor is aligned with respect to the same frame
10	+	aluminum insets that are used to fix the module the ledges in such a
11	+	way the sensor positioning is guaranteed with respect to the support
12	+	structure.\\
13	+
14	+	The double-sided TIB layers and TID rings are equipped with module
15	+	sandwiches capable of a space point measurement and obtained by
16	+	coupling back-to-back a $r\phi$ module and a special ``stereo''
17	+	module with the sensor tilted by $100\mrad$.
18	+
19	+	%The stereo module just
20	+	%differ from the $r\phi$ one in the details needed to cope with the
21	+	%different sensor orientation.
22	+
23	+	{\bf FIX ME: descrizione/tabella dei vari tipi di moduli.}
24	+
25	+	%The readout chip
26	+	%pitch (44$\mu$m) is matched to the sensor pitch via an aluminum deposited glass substrate
27	+	%fanout circuit (pitch
28	+	%adapter). The hybrid circuit, which houses the front-end chips and ancillary
29	+	%electronics, is realized using kapton multilayer technology integrating the power and
30	+	%signal cables. \\
31	+
32	+	A single sided module of the TID ring 1 module shown in
33	+	Fig.~\ref{fig:moduletid}. A TIB double-sided module is shown in Fig.~\ref{fig:moduleds}
34	+
35	+	%\begin{figure}[!htb]
36	+	%\begin{center}
37	+	%  \includegraphics[width=0.60\textwidth]{Figs/moduless.pdf}
38	+	%\end{center}
39	+	%\caption{A 4 chips TIB single sided module mounted on its transportation carrier.}
40	+	%\label{fig:moduless}       % Give a unique label
41	+	%\end{figure}
42
43		\begin{figure}[!htb]
44		\begin{center}
45	<	\includegraphics[width=0.60\textwidth]{Figs/moduless.pdf}
46	<	\end{center}
47	<	\caption{A 4 chips TIB single sided module mounted on its transportation carrier.}
125	<	\label{fig:moduless}       % Give a unique label
126	<	\end{figure}
127	<
128	<	\begin{figure}[!htb]
129	<	\begin{center}
130	<	\includegraphics[width=0.60\textwidth]{Figs/moduleds.pdf}
45	>	\includegraphics[width=0.3\textwidth, height=0.45\textwidth,angle=90]{Figs/module-R1.pdf}
46	>	\hskip 5mm
47	>	\includegraphics[height=0.3\textwidth, width=0.45\textwidth]{Figs/moduleds.pdf}
48		\end{center}
49	<	\caption{A TIB double-sided module. The "stereo" module is visible reflect by a mirror.}
49	>	\caption{A ring 1 TID module (left panel). A TIB double-sided module,
50	>	the ``stereo'' module is visible reflected by a mirror (rigth panel).}
51		\label{fig:moduleds}       % Give a unique label
134	–	\end{figure}
135	–
136	–	\begin{figure}[!htb]
137	–	\begin{center}
138	–	\includegraphics[height=0.60\textwidth,angle=90]{Figs/module-R1.pdf}
139	–	\end{center}
140	–	\caption{ A ring 1 TID module.}
52		\label{fig:moduletid}
53		\end{figure}
54
144	–
145	–	Sensors of the TIB and TID have respectivelly strip lengths of  12 cm and between 9 and 11 cm for TID, are 320 $\mu$m thick
146	–	%{\it verify these lenghts }
147	–	%and of the four innermost rings of the TEC
148	–	and pitches vary between 80 $\mu$m and 120 $\mu$m.
149	–	%These silicon  are made of a single sensor 320 $\mu$m thick.
150	–
151	–	% LD: is this relevant for the TIB/TID integration paper ?
152	–	% ==========================================================
153	–	% In the outer part
154	–	%of the tracker (TOB and three outermost TEC rings) strip length and pitch
155	–	%are increased by about a factor of two with respect to the inner ones. In order
156	–	%to compensate for the noise increase due to the higher inter-strip capacitance
157	–	%(longer strips), a silicon thickness of 500 $\mu$m has been chosen for these larger
158	–	%detectors. \\
159	–
160	–	%All Silicon Strip Sensors are of single sided type and produced from $<100>$
161	–	%Float-zone type 6 inches wafers.
162	–
163	–	Double sided modules are
164	–	realized simply gluing back to back two independent single sided modules: to
165	–	obtain a coarser but adequate resolution on the longitudinal coordinate the so
166	–	called “Stereo” module has the sensor tilted of 100mrad with respect to the
167	–	“R-Phi” one. The “Stereo” sensor and electronics are identical to the “R-Phi”
168	–	ones, the only difference being in the support mechanics and pitch adapters.
169	–
170	–	% LD: is this relevant for the integration paper ?
171	–	% ==================================================
172	–	%To reduce problems due to the radiation damage of the Silicon Strip Sensors
173	–	%the Detector modules will be cooled to a temperature which, on the Silicon Sensor,
174	–	%will reach about -10$^\circ C$.\\
175	–
55		%\subsection{The Front-end Electronics}
56	<	The signals coming from each strip are processed by front-end readout chips
57	<	(APV25) mounted on the multilayer kapton hybrid circuit. The APV25~\cite{ref:apv}
56	>	The multilayer kapton hybrid circuit holds the near front-end
57	>	electronics consisting of four main components: the readout chips,
58	>	APV25 and three ASICs (the Multiplexer, the PLL and the DCU). All
59	>	devices are addressed and controlled by a I$^2$C serial bus.\\
60	>	The signals coming from each strip are processed by four or six front-end readout chips
61	>	(APV25), connected to the silicon sensor strips by means of a glass
62	>	substrate pitch-adapter. The APV25~\cite{ref:apv}
63		is a 128 channel chip built in radiation hard 0.25 $\mu$m
64	<	CMOS technology~\cite{ref:radtol}. Each channel
65	<	consists of a preamplifier coupled to a shaping amplifier which produces a 50ns
66	<	CR-RC pulse shape. The shaper output of each channel is sampled at 40MHz into
67	<	a 192 cell deep pipeline. The pipeline depth allows a programmable
68	<	level 1 trigger latency of up to 4$\mu$s, with 32 locations reserved for buffering
69	<	events awaiting readout. Each pipeline channel is read out by an analogue
70	<	circuitry which can operate in one of two modes. In {\it peak mode} only one
71	<	sample per channel is read (timed to be at the peak of the analogue pulse
72	<	shape). In {\it deconvolution mode}
73	<	\cite{ref:deconvolution} three samples are sequentially read and
74	<	the output is a weighted sum of all three. The deconvolution operation results
75	<	in a re-shaping of the analogue pulse shape to one that peaks at 25 ns and
76	<	returns rapidly to the baseline. This operating mode is particularly important
77	<	for correct bunch crossing identification (i.e. off-time interactions suppression)
78	<	during the high luminosity running
79	<	phase of the LHC. A unity gain inverter, which helps in reducing the common mode
80	<	noise contribution, is included between the preamp and
81	<	shaper and can be switched in or out.
82	<	On receiving a positive level 1 trigger decision the APV25 sends out serially,
83	<	at 20MHz rate, the 128 analogue signals together with information about the
84	<	pipeline address and the chip error status; signals coming from two APV25 are
85	<	interlaced together on a differential line by a Multiplexer chip~\cite{ref:mux}
86	<	which is located
87	<	on the hybrid circuit too.
88	<	Since the chip may not output data for a considerable time when it is waiting for a trigger,
89	<	it is necessary for the DAQ electronics to remain synchronized with the APV25
90	<	when it eventually begins to read out data. To allow for this
91	<	the chip outputs a synchronization pulse, of 25ns duration, called a 'tick mark' every
208	<	70 clock cycles when there is no data to read out.
209	<	The APV25 electrical signals are then converted to optical
210	<	ones in dedicated Analog-Opto Hybrids (AOH\cite{ref:aoh}) few centimeters away from
211	<	the module, and transmitted to the counting room by means of multi-mode
212	<	optical fibers~\cite{ref:opto}, where they are digitized~\cite{ref:fed}.
213	<	The LHC 40MHz clock, which
214	<	drives the APV25 sampling can be delayed at the single module level by
215	<	means of a PLL (phase lock loop) chip\cite{ref:pll} to take into account the
216	<	different cable lengths and distances from the interaction point. \\
217	<	The Detector Control Unit (DCU) is a rad-hard ASIC, mounted on the
218	<	front-end hybrid. This chip
219	<	contains an eight channel analog to digital converter,
64	>	CMOS technology~\cite{ref:radtol}. Each channel consists of a
65	>	preamplifier coupled to a CR-RC 50ns shaper. The shaper output is sampled at 40MHz into
66	>	a 192 cells pipeline that allows trigger latencies up to 4$\mu$s.\\
67	>	The APV25 can operate in {\it peak mode} or in {\it deconvolution
68	>	mode}. In the former the shaping time is $50\ns$; in the latter, by
69	>	using a deconvolution filter~\cite{ref:deconvolution}, the
70	>	effective shaping time is 25ns. In addition, there is also the
71	>	possibility to switch on (Inv) or off an inverter to fully exploit
72	>	the dynamic range of the preamplifier with signals of both
73	>	polarity. Standard operation mode for Silicon Sensor is with
74	>	inverter on.
75	>	{\bf FIX ME: ma serve??? Nel seguito non si fa mai menzione dei vari
76	>	modi di funzionamento dell'APV - forse da aggiungere nela
77	>	descrizione del ped-noi run?}
78	>
79	>	On receiving a level 1 trigger the APV25 sends out serially
80	>	%, at 20MHz rate,
81	>	the 128 analogue signals together with information about the
82	>	pipeline address and the chip error status; two APV25 are multiplexed
83	>	on a differential line by the Multiplexer chip~\cite{ref:mux}.
84	>	In absence of data to stream out, for synchronization purposes, the
85	>	APV issues a 25ns pulse called ``tick mark''
86	>	with a period of 70 clock cycles.\\
87	>	The PLL chip\cite{ref:pll} allows the clock to be delayed to
88	>	compensate for path differences of control signals and for any
89	>	electronics delay. The PLL also decodes the trigger signals that are
90	>	encoded on the clock line.\\
91	>	The Detector Control Unit (DCU) contains an eight-channel ADC,
92		two constant current sources and a temperature sensor. It
93		monitors two sets of thermistors, one on the sensor
94		and one on the hybrid, its own internal temperature, the
95		silicon sensor bias current and the two (1.25 V and
96	<	2.5 V) low voltages.\\
97	<	Each DCU has a unique hardware identification
98	<	number (called \textit{DCU Hardware ID}) that can also be read through the $I^2C$ interface.
99	<	This number can be used to identify each module and
100	<	to act as a link between the construction database, that
101	<	stores the module information,
102	<	and the online databases, storing information during data taking.
103	<
104	<	\subsection{The off-Module Electronics}
105	<	\subsubsection{AOH}
106	<
107	<	The electric to optical conversion is done by radiation hard lasers~\cite{Gill:2005ui}.
108	<	These devices sit on a dedicated board, called Analog Opto-Hybrid, which is
109	<	fixed on a ledge glued on the cooling pipe very close to the silicon module.
110	<	The electrical signals arrive to the AOH through the module front-end hybrid
111	<	kapton cable tail which carries the AOH power lines too.
112	<	The AOH can hold up to three lasers (only two are mounted for single sided 4 APV chips
113	<	modules) and their control hardware.\\
114	<	The on-board control logic is used to drive the lasers: it has an $I^2C$
115	<	control register for each laser
116	<	which is split in a 2-bit section (GAIN: 0$\div$3) and a 7-bit section (BIAS: 0$\div$127).
117	<	The GAIN value can be used to compensate the loss of signal on the fiber link
118	<	and optical connections from AOHs to FEDs.
119	<	During normal operation, if no damage was done to the line and ideal connections,
120	<	it is normally set to 1. The actual gain
121	<	of the AOH is not proportional to the GAIN parameter, as the four
122	<	possible nominal gains are: 0.5, 0.75, 1, 1.25 (normalized w.r.t. GAIN=3).
123	<	The BIAS parameter regulates the current threshold for the laser diodes.
124	<	Its optimal value strongly depends on temperature and also on irradiation.
253	<
254	<	Each AOH has two (single sided modules)  or three (double sided modules)
255	<	two meter long pig-tail optical fibres ending with a connector
256	<
257	<	\subsubsection{CCU}
258	<
259	<	{\it manca referenza }
260	<
261	<	The module electronics is controlled by a set of signals
262	<	(clock, trigger, $I^2C$ lines) which are dispatched to them via a
263	<	token ring structured circuitry ("control ring").
264	<	CCUs are the nodes of this structure. They receive instructions from the external
265	<	FEC (front-End Controller)
266	<	either directed to themselves or to the $I^2C$ devices connected to them. The first case is used
267	<	for example to read the Status Register of the CCU or to raise its output PIA reset lines.
268	<	While in the latter case
269	<	commands are translated to the $I^2C$ protocol and forwarded to the
270	<	other devices located on the sensor modules or AOH; in case of
271	<	a reply from the $I^2C$ device, the reverse process is done by the CCU, which addresses the
272	<	information to the FEC.
273	<	The CCU device sits on a CCU-Module (or CCUM) which carries also buffering chips and a DCU.
274	<
275	<
276	<	\subsubsection{Mother Cable}
277	<
278	<	{\it manca referenza }
279	<
280	<
281	<	In the TIB/TID a multi-layer kapton copper cable ("Mother Cable", see Fig.~\ref{fig:fotomc})
282	<	is mounted on the carbon fiber shell underneath the
283	<	modules. A full description of the mother-cable can be found in~\cite{ref:mc}.
284	<
285	<	It carries the $I^2C$ serial data (SDA)
286	<	and clock (SCL) lines,
287	<	a hard reset (PIA reset) line and the
288	<	LHC clock for each module. CCUs in the TIB can be connected to 3 or 6 modules\footnote{Actually
289	<	to 3 single-sided or double-sided modules, but to the Control System point of view a
290	<	double-sided module is seen as a pair of independent modules.} while for TID are connected to
291	<	6  modules (3 double-side modules) for R1 and R2 and to 5 modules for R3.
292	<
293	<	\begin{figure}
294	<	\begin{center}
295	<	\includegraphics[width=0.85\textwidth]{Figs/mothercable.pdf}
296	<	\end{center}
297	<	\caption{A mother cable mounted on a shell. In the two upper boxes, the detail of the CCU
298	<	installed on MC and the connectors at the edge of the MC.}
299	<	\label{fig:fotomc}
300	<	\end{figure}
301	<	Moreover this cable is used to power the modules (1.25~V, 2.5~V, high voltage bias line and
302	<	common return).\\
303	<	The mother cable receives LV and HV power for the modules, power and signals for the CCU, via three sockets located at the edge; then hosts a socket to hold and feed the CCU module and serves  each module with a couple
304	<	of connectors (LV \& $I^2C$ and HV).
96	>	2.5 V) low voltages. Each DCU has a unique hardware identification
97	>	number (called \textit{DCU Hardware ID}) that can also be read through
98	>	the $I^2C$ interface. By means of this number each module has an
99	>	unique identification.
100	>
101	>	\subsection{The Analog Opto Hybrid}
102	>
103	>	The Analog-Opto Hybrids~\cite{ref:aoh} (AOH) performs the
104	>	electrical-to-optical conversion of the electrical signals of the two
105	>	or three APV25 pairs, depending on the module type, by means of
106	>	radiation hard lasers~\cite{Gill:2005ui}. There is one AOH
107	>	per module, sitting on a ledge glued on the cooling pipe very close to
108	>	the silicon module hybrid. Multi-mode optical fiber~\cite{ref:opto}
109	>	transport the signal to the FEDs~\cite{ref:fed} for the
110	>	digitization. Each AOH has two or three two meter long pig-tail
111	>	optical fibres ending with an optical plug.\\
112	>	The electrical signals arrive to the AOH through hybrid
113	>	kapton cable. The AOH is powered by the same cable.
114	>	By means of the AOH control logic the laser working parameters GAIN
115	>	and BIAS can be set via $I^2C$  control registers.
116	>	The GAIN parameter can be used to compensate the loss of signal
117	>	on the optical link to the FED input. The GAIN parameter has four
118	>	possible values, 0, 1, 2, 3, corresponding to a nominal
119	>	gain value of 0.5, 0.75, 1, 1.25, respectively, normalized at
120	>	GAIN=3. During normal operation, if no damage was done to the line and
121	>	ideal connections, it is normally set to 1.
122	>	The BIAS parameter regulates the current threshold for the laser
123	>	diodes and can be set in the range 0$\div$127. The optimal value
124	>	strongly depends on temperature and also on irradiation.
125
126	<	For the TIB one mother cable serves a full string, while for the TID serves a 90 degrees sector.
307	<
308	<
309	<	%%%%%%%%%% qui l'ho un po' cambiato. C.G.
310	<	%\subsubsection{DOH}
311	<
312	<	%\subsubsection{DOHM}
313	<
314	<	\subsubsection{Control Ring}
126	>	\subsection{The Control Ring}
127		\label{fig:ctrlring}
128
129	<	{\it manca referenza }
130	<
131	<	A control ring is an electro-optical circuitry that interfaces the front-end electronics to the
132	<	tracker control system.
133	<	The control ring is optically driven by a FEC (Front-End Controller) module~\cite{ref:opto}
134	<	located outside  the tracker in the experiment control room.
135	<	The FEC optical signals are converted into LVDS~\cite{ref:lvds}
136	<	electrical signals by two DOHs
137	<	(Digital Opto-Hybrid) that
138	<	send clock, trigger, and control signals to the token ring of CCUs.
139	<	The DOHs are physically located on a board (DOHM~\cite{ref:dohm}) that provides up to 15 ports
140	<	(7 on the main DOHM board plus 8 on its
129	>	The control of the modules front-end electronic is implemented by means of a
130	>	hierarchical structure organized in groups of modules~\cite{ref:dohm}. Each group is
131	>	controlled by a Communication and Control Unit (CCU) taht represents a
132	>	``node'' in a ``token-ring'' formed by several daisy-chained CCUs and
133	>	known as {\it control ring}. The control ring is mastered by a Front End
134	>	Controller, FEC~\cite{ref:opto}, located outside the experiment by
135	>	means of optical signals. The entire TIB and TID contains roughly 100
136	>	Control Rings.
137	>
138	>	\begin{description}
139	>	\item[Digital Opto Hybrid Module] The FEC optical signals are converted into electrical signals by two DOHs
140	>	(Digital Opto-Hybrid) that send clock, trigger, and control signals to
141	>	the token ring of CCUs. The DOHs are physically located on a board,
142	>	Digital Opto Hybrid Module~\cite{ref:dohm} (DOHM), that provides up to
143	>	15 ports (7 on the main DOHM board plus 8 on its
144		secondary extension or AUX) to implement the token ring. Each port
145	<	connects the DOHM or the AUX to a CCU located on the Mother Cable head via a 26 poles flat cable.
146	<	Since the failure of a single node on a token-ring structure may
147	<	affect the functionality of all the devices connected to the ring, a
148	<	redundant architecture has been implemented for the connections. In Fig.~\ref{fig:redundancy}
149	<	the structure of the
150	<	redundancy circuit is shown. Each CCU is connected to the two nearby CCUs through the primary
151	<	circuit (``A'' in Fig.~\ref{fig:redundancy}) and to the second next CCUs through the secondary
152	<	circuit (``B'').
153	<	In order to handle the special case of  a failure either in the last CCU or in the DOH A,
154	<	a ``dummy CCU'' is placed on the DOHM board.
155	<	As shown in Fig.~\ref{fig:redundancy}, a failing CCU  can thus easily bypassed using the
341	<	secondary circuit.
145	>	connects the DOHM to a CCU located on the Mother Cable head
146	>	via a 26 poles flat cable.
147	>	To cope with possible CCU failures that would affect the entire ring, the
148	>	control ring features the so called {\it redundancy} by means of
149	>	a clever layout, shown in Fig.~\ref{fig:redundancy}, that exploits the
150	>	two input/output replicas of the CCUs: each CCU is connected to the
151	>	two nearby CCUs through the primary circuit (``A'') and to the second
152	>	next CCUs through the secondary circuit (``B'') by which a failing CCU
153	>	can be bypassed. To cope with the failure either of the last
154	>	CCU or of the primary DOH (A), the DOHM holds a ``dummy CCU'' and a
155	>	spare DOH (B).
156		\begin{figure}
157		\begin{center}
158		\includegraphics[width=0.85\textwidth]{Figs/default_redundancy.pdf}
#	Line 346 | Line 160 | secondary circuit.
160		\caption{Scheme of primary and secondary circuit of the ring. }
161		\label{fig:redundancy}
162		\end{figure}
163	<	If no CCU is connected to a given DOHM port, a special plug must be  inserted in order to ensure the
164	<	continuity of the  primary and secondary control circuits. The redundancy properties of the system
165	<	are preserved by observing two ``rules'', i.e. a) if an even number of plugs is needed,
166	<	plugs must be organized in  pairs, each pair having the two plugs inserted in consecutive ports, b)
167	<	if  an odd number of plugs is needed, one plug must be placed in the last DOHM port
168	<	(before the dummy CCU), and the remaining ones following the previous rule.
169	<
170	<
163	>	If no CCU is connected to a given DOHM port, a special loop-back plug
164	>	must be  inserted in order to ensure the continuity of the primary
165	>	and secondary control circuits.
166	>	%The redundancy properties of the system
167	>	%are preserved by observing two ``rules'', i.e. a) if an even number of plugs is needed,
168	>	%plugs must be organized in  pairs, each pair having the two plugs inserted in consecutive ports, b)
169	>	%if  an odd number of plugs is needed, one plug must be placed in the last DOHM port
170	>	%(before the dummy CCU), and the remaining ones following the previous rule.
171	>	\item[CCU] The CCU serves a group of modules and performs the following tasks:
172	>	distributes the clock/trigger and the hard reset to the modules;
173	>	dispatches the instructions received from the
174	>	FEC to the modules APV25s and the other ASICS via $I^2C$ or
175	>	vice-versa, i.e. addresses the readings from the $I^2C$ devices to the FEC.
176	>	Each CCU device sits on a CCU-Module (or CCUM) which carries also
177	>	buffering chips and a DCU. Each CCU has an hardware address
178	>	configurable by means of appropriate solder pads on the CCUM board to
179	>	be shorted or not by a SMD pull up resistor.
180	>	%either directed to themselves or to the devices connected to them. The first case is used
181	>	%for example to read the Status Register of the CCU or to raise its output PIA reset lines.
182	>	%While in the latter case
183	>	%commands are translated to the $I^2C$ protocol and forwarded to the
184	>	%other devices located on the sensor modules or AOH; in case of
185	>	%a reply from the $I^2C$ device, the reverse process is done by the CCU, which addresses the
186	>	%information to the FEC.
187	>	\end{description}
188	>
189	>	\subsection{The Mother Cable}
190	>	The  electrical connections between a group of modules served by the
191	>	same CCU are done by the {\it Mother Cable}~\cite{ref:mc}, a flexible
192	>	multi-layer kapton copper circuit. An example is shown in
193	>	Fig.~\ref{fig:fotomc}. The mother cable is mounted on the carbon fiber
194	>	support structure underneath the modules.
195	>	The mother cable holds a CCUM and distributes the $I^2C$ serial data (SDA)
196	>	and clock (SCL) lines, the hard reset (PIA reset) line and the
197	>	clock/trigger to each module.
198	>	The mother cable is connected to a Power Supply unit via two sockets
199	>	located at the edge and feeds the modules with low voltages (1.25~V,
200	>	2.5~V) and the high voltage.
201	>
202	>	In the TIB the mother cable coincides
203	>	with the string, i.e. six modules
204	>	(three double sides assemblies) in L1 and L2 and three modules in L3
205	>	and L4. In the TID each mother cable serves a 90-degrees sector,
206	>	i.e. six modules (three double-sided assemblies) in R1 and R2 and
207	>	five modules in R3.
208
209	+	\begin{figure}
210	+	\begin{center}
211	+	\includegraphics[width=0.85\textwidth]{Figs/mothercable.pdf}
212	+	\end{center}
213	+	\caption{A mother cable mounted on a shell. In the two upper boxes, the detail of the CCU
214	+	installed on MC and the connectors at the edge of the MC.}
215	+	\label{fig:fotomc}
216	+	\end{figure}
217
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