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\section{The TIB/TID Components} |
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\section{The Integration Components} |
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\label{sec:Components} |
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Full views of a finished half of the TIB and a TID Disk are shown in Fig.~\ref{fig:tibtid}. |
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This section describes the main TIB and TID components: detailed description will be made for items which are |
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of particular importance for the integration activities, both for assemblies and tests. |
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|
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\begin{figure}[!htb] |
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\begin{center} |
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\includegraphics[height=0.5\textwidth]{Figs/TIB-assembled.pdf} |
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\includegraphics[width=0.5\textwidth, angle=90]{Figs/TID-disk.pdf} |
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\end{center} |
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\caption{Half of TIB assembled and one TID disk on the left and on the right respectively. The 4 shells |
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structure is visible for the TIB; the 3 rings structure is visible for the Disk.} |
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\label{fig:tibtid} % Give a unique label |
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\end{figure} |
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|
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Table~\ref{table:layers} summarize the number of the different components for the several layers/rings |
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of the TIB/TID. |
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\subsection{The Silicon Module} |
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The TIB and TID modules (table~\ref{table:modules}) |
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consist of a carbon fiber support |
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frame that holds a single silicon |
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sensor~\cite{ref:mask}\cite{ref:sensors} and the front-end electronics |
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hybrid circuit~\cite{ref:hybrid}. |
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These detectors are produced from individual, 320~$\mu$m thick, sensors. |
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All silicon strip sensors are of the |
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single-sided ``p-on-n'' type |
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with integrated decoupling capacitors, aluminium readout strips |
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and polysilicon bias resistors. |
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The sensor is aligned with respect to the same frame |
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aluminum inserts that are used to fix the module the ledges in such a |
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way the sensor positioning is guaranteed with respect to the support |
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structure~\cite{ref:assembly}.\\ |
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Double-sided detectors are built by simply assembling two independent |
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single-sided modules (``R-Phi'' and ``Stereo'') back to back. |
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The double-sided TIB layers and TID rings are equipped with module |
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sandwiches capable of a space point measurement and obtained by |
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coupling back-to-back a ``R-Phi'' module and a special ``Stereo'' |
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module with the sensor tilted by $100\mrad$ with respect to the other. |
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The stereo sensor and electronics are identical to the R-Phi ones, the only |
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difference being in the support mechanics and pitch adapters. \\ |
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|
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|
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%The stereo module just |
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%differ from the $r\phi$ one in the details needed to cope with the |
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%different sensor orientation. |
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\begin{table}[!htb] |
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\begin{center} |
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\begin{tabular}{|l||c|c|c|c|c|c|c|} |
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\caption[smallcaption]{Details on the different TIB/TID modules. } |
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\label{table:modules} |
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%\begin{tabular}{|l||c|c|c|c|c|c|c|} |
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\begin{tabular}{|l|ccccc|} |
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\hline |
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Layer & \# mechanical & \# cooling & DS/SS & \# of modules & \# of channels & \# Control & \# Mother \\ |
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& structures & circuits & layer & total & per module & Rings & Cables \\ |
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Module & pitch ($\mu$m) & Assembly &Active area & \# of APVs & \# of channels \\ |
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type & & type &$cm^2$ & & per module \\ |
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\hline |
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\hline |
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TIB L1 & 4 shells & & DS & & & & \\ |
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TIB L2 & 4 shells & & DS & & & & \\ |
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TIB L3 & 4 shells & & SS & & & & \\ |
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TIB L4 & 4 shells & & SS & & & & \\ |
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TID R1 & 6 rings & 24 & DS & 288 & 768 & 12 & 48 \\ |
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TID R2 & 6 rings & 24 & DS & 288 & 768 & 12 & 48 \\ |
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TID R3 & 6 rings & 24 & SS & 240 & 512 & 12 & 48 \\ |
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% \hline |
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TIB Layer 1-2 $r-/phi$ & 80 & DS & 35 & 6 & 768 \\ |
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TIB Layer 1-2 stereo & 80 & DS & 35 & 6 & 768 \\ |
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TIB Layer 3-4 $r-/phi$ & 120 & SS & 35 & 4 & 512 \\ |
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TID Ring 1 $r-/phi$ & 81-119 & DS & 85 & 6 & 768 \\ |
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TID Ring 1 stereo & 81-119 & DS & 85 & 6 & 768 \\ |
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TID Ring 2 $r-/phi$ & 81-119 & DS & 88 & 6 & 768 \\ |
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TID Ring 2 stereo & 81-119 & DS & 88 & 6 & 768 \\ |
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TID Ring 3 $r-/phi$ & 123-158 & SS & 79 & 4 & 512 \\ |
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\hline |
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\end{tabular} |
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\caption[smallcaption]{ Details on the different layers/rings of the TIB/TID. } |
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\label{table:layers} |
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\end{center} |
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\end{table} |
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|
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%%{\bf FIX ME: descrizione/tabella dei vari tipi di moduli.} |
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\subsection{Mechanical Structures} |
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The TIB support structure was designed structured as 4 concentric layers |
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and realized using mainly carbon fiber. Each of these layers |
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is made up of four half-cylinder (called "shells") |
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being split vertically at $z=0$ and horizontally at $y=0$. |
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Each shell hosts services both on its external and its internal surface. |
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Modules and associated services, that are on the same side of a shell and at the same $\phi$ coordinate |
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constitute a \textit{string}. |
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%A TIB shell is shown on Fig.~\ref{fig:tibshell}). |
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|
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%Each cooling loop hosts three modules placed in a straight row, which is called a |
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%A string of modules is connected to the same CCU, thus forming a control branch. |
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|
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%\begin{figure} |
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%\centering |
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%\includegraphics[width=\textwidth]{ } |
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%\caption{TIB shell: are visible the internal and external parts, the cooling pipes and the string} |
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%\label{fig:tibshell} |
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%The readout chip |
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%pitch (44$\mu$m) is matched to the sensor pitch via an aluminum deposited glass substrate |
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%fanout circuit (pitch |
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%adapter). The hybrid circuit, which houses the front-end chips and ancillary |
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%electronics, is realized using kapton multilayer technology integrating the power and |
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%signal cables. \\ |
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|
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A single sided module of the TID ring 3 and a TIB double-sided module |
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are shown in Fig.~\ref{fig:moduleds}. |
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|
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%\begin{figure}[!htb] |
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%\begin{center} |
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% \includegraphics[width=0.60\textwidth]{Figs/moduless.pdf} |
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%\end{center} |
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%\caption{A 4 chips TIB single sided module mounted on its transportation carrier.} |
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%\label{fig:moduless} % Give a unique label |
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%\end{figure} |
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|
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The 6 TID disks are all identical and each one is made out of three rings. Each ring consists of |
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a support mechanical structure made of an annular carbon fiber honeycomb, hosting modules and services on both sides to decrease the density and therefore providing a better accessibility during ring integration and disk assembly. |
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|
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Each TID+ and TID- is obtained by inserting, positioning and fixing each disk into a carbon fiber cylinder called {\it Service Cylinder}. Each Service Cylinder has several holes at the position of disk, in order to allow the connection of the power lines and to route out all the fibers of the disk. The service Cylinder is also used to connect mechanically TIB+/- and TID+/-, |
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and to route out the services of the TIB and of the TID. |
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|
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%\begin{figure} |
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%\centering |
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%\includegraphics[width=\textwidth]{ } |
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%\caption{TID ring } |
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%\label{fig:tidring} |
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%\end{figure} |
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|
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|
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The cooling in the TIB/TID is distributed via aluminum circuits called cooling pipes |
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that are bent into loops and soldered to inlet/outlet manifolds near a large flange. |
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The thermal connection between pipes and sensor modules is made with Aluminum ledges which are |
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precisely glued on the carbon fiber support structure and in good thermal contact with the pipes. |
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On each ledge there are two threaded M1 holes onto which the modules are tightened. |
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Precisely drilled slots, coaxial with the threaded holes, are the reference point where |
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insets are stick in providing mechanical reference for modules. An example for a TIB module |
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is shown in Fig.~\ref{fig:module_cooling}). |
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|
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|
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\begin{figure} |
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\centering |
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\includegraphics[width=\textwidth]{Figs/module_cooling.pdf} |
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\caption{Module Cooling . |
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\textbf{Upper picture:} a whole cooling loop with six ledges to hold three modules and three |
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smaller ledges to hold Analog Opto-Hybrids (two more cooling loops are partially visible). |
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\textbf{Lower picture:} a detail of a cooling loop. The cooling fluid direction |
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is evidenced with blue arrows, and the precision insets for module insertion are circled in |
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red. A module mounted on the nearby position is also visible.} |
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\label{fig:module_cooling} |
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\end{figure} |
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|
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|
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\subsection{The Silicon Module} |
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The silicon module design has been kept as simple as possible to ease their |
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mass production and integration. In TIB and TID the module hosts a single silicon sensor~\cite{ref:mask}\cite{ref:sensors} glued on a carbon fiber support |
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frame which also holds the front-end electronics hybrid. The sensor is aligned with respect to the same frame aluminum insets that are used to mount the module on the shell: this choice guarantee the best reproducibility |
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of the sensor position in the global shell coordinate system.\\ |
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The readout chip |
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pitch (44$\mu$m) is matched to the sensor pitch via an aluminum deposited glass substrate |
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fanout circuit (pitch |
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adapter). The hybrid circuit, which houses the front-end chips and ancillary |
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electronics, is realized using kapton multilayer technology integrating the power and |
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signal cables. \\ |
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Fig~\ref{fig:moduless} and \ref{fig:moduleds} show a TIB single and double-sided module |
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respectively. Fig.~\ref{fig:moduletid} show a R1 TID module. |
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|
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{\it Commento LD: Dobbiamo aggiungere delle foto di tutte le geometrie ? |
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} |
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|
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|
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\begin{figure}[!htb] |
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\begin{center} |
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\includegraphics[width=0.60\textwidth]{Figs/moduless.pdf} |
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\end{center} |
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\caption{A 4 chips TIB single sided module mounted on its transportation carrier.} |
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\label{fig:moduless} % Give a unique label |
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\end{figure} |
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|
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\begin{figure}[!htb] |
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\begin{center} |
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\includegraphics[width=0.60\textwidth]{Figs/moduleds.pdf} |
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\includegraphics[width=0.3\textwidth, height=0.45\textwidth,angle=90]{Figs/module-R1.pdf} |
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\hskip 5mm |
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\includegraphics[height=0.3\textwidth, width=0.45\textwidth]{Figs/moduleds.pdf} |
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\end{center} |
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\caption{A TIB double-sided module. The "stereo" module is visible reflect by a mirror.} |
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\caption{A ring 3 TID module (left panel). A TIB double-sided assembly, |
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the ``stereo'' module is visible reflected by a mirror (rigth panel).} |
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\label{fig:moduleds} % Give a unique label |
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\end{figure} |
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|
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\begin{figure}[!htb] |
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\begin{center} |
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\includegraphics[height=0.60\textwidth,angle=90]{Figs/module-R1.pdf} |
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\end{center} |
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\caption{ A ring 1 TID module.} |
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\label{fig:moduletid} |
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\end{figure} |
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|
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|
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Sensors of the TIB and TID have respectivelly strip lengths of 12 cm and between 9 and 11 cm for TID, are 320 $\mu$m thick |
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%{\it verify these lenghts } |
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%and of the four innermost rings of the TEC |
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and pitches vary between 80 $\mu$m and 120 $\mu$m. |
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%These silicon are made of a single sensor 320 $\mu$m thick. |
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|
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% LD: is this relevant for the TIB/TID integration paper ? |
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% ========================================================== |
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% In the outer part |
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%of the tracker (TOB and three outermost TEC rings) strip length and pitch |
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%are increased by about a factor of two with respect to the inner ones. In order |
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%to compensate for the noise increase due to the higher inter-strip capacitance |
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%(longer strips), a silicon thickness of 500 $\mu$m has been chosen for these larger |
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%detectors. \\ |
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|
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%All Silicon Strip Sensors are of single sided type and produced from $<100>$ |
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%Float-zone type 6 inches wafers. |
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|
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Double sided modules are |
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realized simply gluing back to back two independent single sided modules: to |
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obtain a coarser but adequate resolution on the longitudinal coordinate the so |
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called “Stereo” module has the sensor tilted of 100mrad with respect to the |
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“R-Phi” one. The “Stereo” sensor and electronics are identical to the “R-Phi” |
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ones, the only difference being in the support mechanics and pitch adapters. |
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|
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% LD: is this relevant for the integration paper ? |
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% ================================================== |
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%To reduce problems due to the radiation damage of the Silicon Strip Sensors |
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%the Detector modules will be cooled to a temperature which, on the Silicon Sensor, |
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%will reach about -10$^\circ C$.\\ |
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|
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%\subsection{The Front-end Electronics} |
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The signals coming from each strip are processed by front-end readout chips |
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(APV25) mounted on the multilayer kapton hybrid circuit. The APV25~\cite{ref:apv} |
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is a 128 channel chip built in radiation hard 0.25 $\mu$m |
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CMOS technology~\cite{ref:radtol}. Each channel |
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consists of a preamplifier coupled to a shaping amplifier which produces a 50ns |
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CR-RC pulse shape. The shaper output of each channel is sampled at 40MHz into |
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a 192 cell deep pipeline. The pipeline depth allows a programmable |
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level 1 trigger latency of up to 4$\mu$s, with 32 locations reserved for buffering |
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events awaiting readout. Each pipeline channel is read out by an analogue |
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circuitry which can operate in one of two modes. In {\it peak mode} only one |
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sample per channel is read (timed to be at the peak of the analogue pulse |
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shape). In {\it deconvolution mode} |
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\cite{ref:deconvolution} three samples are sequentially read and |
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the output is a weighted sum of all three. The deconvolution operation results |
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in a re-shaping of the analogue pulse shape to one that peaks at 25 ns and |
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returns rapidly to the baseline. This operating mode is particularly important |
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for correct bunch crossing identification (i.e. off-time interactions suppression) |
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during the high luminosity running |
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phase of the LHC. A unity gain inverter, which helps in reducing the common mode |
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noise contribution, is included between the preamp and |
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shaper and can be switched in or out. |
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On receiving a positive level 1 trigger decision the APV25 sends out serially, |
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at 20MHz rate, the 128 analogue signals together with information about the |
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pipeline address and the chip error status; signals coming from two APV25 are |
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interlaced together on a differential line by a Multiplexer chip~\cite{ref:mux} |
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which is located |
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on the hybrid circuit too. |
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Since the chip may not output data for a considerable time when it is waiting for a trigger, |
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it is necessary for the DAQ electronics to remain synchronized with the APV25 |
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when it eventually begins to read out data. To allow for this |
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the chip outputs a synchronization pulse, of 25ns duration, called a 'tick mark' every |
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70 clock cycles when there is no data to read out. |
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The APV25 electrical signals are then converted to optical |
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ones in dedicated Analog-Opto Hybrids (AOH\cite{ref:aoh}) few centimeters away from |
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the module, and transmitted to the counting room by means of multi-mode |
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optical fibers~\cite{ref:opto}, where they are digitized~\cite{ref:fed}. |
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The LHC 40MHz clock, which |
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drives the APV25 sampling can be delayed at the single module level by |
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means of a PLL (phase lock loop) chip\cite{ref:pll} to take into account the |
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different cable lengths and distances from the interaction point. \\ |
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The Detector Control Unit (DCU) is a rad-hard ASIC, mounted on the |
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front-end hybrid. This chip |
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contains an eight channel analog to digital converter, |
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The multilayer kapton hybrid circuit holds the module front-end |
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electronics consisting of four main components: the readout chips |
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(APV25) and three ASICs (the Multiplexer, the PLL and the DCU). All |
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devices are addressed and controlled by a I$^2$C serial bus~\cite{ref:i2c}.\\ |
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The signals coming from each strip are processed by four or six front-end |
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readout chips, connected to the silicon sensor strips by means of a glass |
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substrate pitch-adapter. The APV25~\cite{ref:apv} |
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is a 128 channel chip built in radiation tolerant 0.25 $\mu$m |
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CMOS technology~\cite{ref:radtol}. Each channel consists of a |
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preamplifier coupled to a CR-RC 50ns shaper. The shaper output is sampled at 40MHz into |
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a 192 cells pipeline that allows trigger latencies up to 4$\mu$s.\\ |
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The APV25 can operate in {\it peak mode} or in {\it deconvolution |
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mode}. In the former the shaping time is $50\ns$; in the latter, by |
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using a deconvolution filter~\cite{ref:deconvolution}, the |
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effective shaping time is 25ns. In addition, there is also the |
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possibility to switch on or off an inverter stage which slightly |
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decreases the common mode noise contribution. |
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% Standard operation mode for Silicon Sensor is with |
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% inverter on. |
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%%{\bf FIX ME: ma serve??? Nel seguito non si fa mai menzione dei vari |
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%% modi di funzionamento dell'APV - forse da aggiungere nela |
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%% descrizione del ped-noi run?} |
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|
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On receiving a level 1 trigger the APV25 sends out serially |
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%, at 20MHz rate, |
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the 128 analogue signals together with information about the |
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pipeline address and the chip error status; two APV25 are multiplexed |
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on a differential line by the Multiplexer chip~\cite{ref:mux}. |
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In absence of data to stream out, for synchronization purposes, the |
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APV25 issues a 25ns pulse called ``tick mark'' |
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with a period of 70 clock cycles.\\ |
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The Phase Locked Loop (PLL) chip~\cite{ref:pll} allows the clock to be delayed by 1.04ns |
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steps, to |
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compensate for path differences of control signals and for any |
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electronics delay. The PLL also decodes the trigger signals that are |
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encoded on the clock line.\\ |
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The Detector Control Unit (DCU)~\cite{ref:dcu} contains an eight-channel ADC, |
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two constant current sources and a temperature sensor. It |
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monitors two sets of thermistors, one on the sensor |
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and one on the hybrid, its own internal temperature, the |
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silicon sensor bias current and the two (1.25 V and |
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2.5 V) low voltages.\\ |
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Each DCU has a unique hardware identification |
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number (called \textit{DCU Hardware ID}) that can also be read through the $I^2C$ interface. |
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This number can be used to identify each module and |
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to act as a link between the construction database, that |
| 136 |
< |
stores the module information, |
| 137 |
< |
and the online databases, storing information during data taking. |
| 138 |
< |
|
| 139 |
< |
\subsection{The off-Module Electronics} |
| 140 |
< |
\subsubsection{AOH} |
| 141 |
< |
|
| 142 |
< |
The electric to optical conversion is done by radiation hard lasers~\cite{Gill:2005ui}. |
| 143 |
< |
These devices sit on a dedicated board, called Analog Opto-Hybrid, which is |
| 144 |
< |
fixed on a ledge glued on the cooling pipe very close to the silicon module. |
| 145 |
< |
The electrical signals arrive to the AOH through the module front-end hybrid |
| 146 |
< |
kapton cable tail which carries the AOH power lines too. |
| 147 |
< |
The AOH can hold up to three lasers (only two are mounted for single sided 4 APV chips |
| 148 |
< |
modules) and their control hardware.\\ |
| 149 |
< |
The on-board control logic is used to drive the lasers: it has an $I^2C$ |
| 150 |
< |
control register for each laser |
| 151 |
< |
which is split in a 2-bit section (GAIN: 0$\div$3) and a 7-bit section (BIAS: 0$\div$127). |
| 152 |
< |
The GAIN value can be used to compensate the loss of signal on the fiber link |
| 153 |
< |
and optical connections from AOHs to FEDs. |
| 154 |
< |
During normal operation, if no damage was done to the line and ideal connections, |
| 155 |
< |
it is normally set to 1. The actual gain |
| 156 |
< |
of the AOH is not proportional to the GAIN parameter, as the four |
| 157 |
< |
possible nominal gains are: 0.5, 0.75, 1, 1.25 (normalized w.r.t. GAIN=3). |
| 158 |
< |
The BIAS parameter regulates the current threshold for the laser diodes. |
| 159 |
< |
Its optimal value strongly depends on temperature and also on irradiation. |
| 160 |
< |
|
| 161 |
< |
Each AOH has two (single sided modules) or three (double sided modules) |
| 255 |
< |
two meter long pig-tail optical fibres ending with a connector |
| 256 |
< |
|
| 257 |
< |
\subsubsection{CCU} |
| 258 |
< |
|
| 259 |
< |
{\it manca referenza } |
| 260 |
< |
|
| 261 |
< |
The module electronics is controlled by a set of signals |
| 262 |
< |
(clock, trigger, $I^2C$ lines) which are dispatched to them via a |
| 263 |
< |
token ring structured circuitry ("control ring"). |
| 264 |
< |
CCUs are the nodes of this structure. They receive instructions from the external |
| 265 |
< |
FEC (front-End Controller) |
| 266 |
< |
either directed to themselves or to the $I^2C$ devices connected to them. The first case is used |
| 267 |
< |
for example to read the Status Register of the CCU or to raise its output PIA reset lines. |
| 268 |
< |
While in the latter case |
| 269 |
< |
commands are translated to the $I^2C$ protocol and forwarded to the |
| 270 |
< |
other devices located on the sensor modules or AOH; in case of |
| 271 |
< |
a reply from the $I^2C$ device, the reverse process is done by the CCU, which addresses the |
| 272 |
< |
information to the FEC. |
| 273 |
< |
The CCU device sits on a CCU-Module (or CCUM) which carries also buffering chips and a DCU. |
| 274 |
< |
|
| 275 |
< |
|
| 276 |
< |
\subsubsection{Mother Cable} |
| 277 |
< |
|
| 278 |
< |
{\it manca referenza } |
| 279 |
< |
|
| 280 |
< |
|
| 281 |
< |
In the TIB/TID a multi-layer kapton copper cable ("Mother Cable", see Fig.~\ref{fig:fotomc}) |
| 282 |
< |
is mounted on the carbon fiber shell underneath the |
| 283 |
< |
modules. A full description of the mother-cable can be found in~\cite{ref:mc}. |
| 284 |
< |
|
| 285 |
< |
It carries the $I^2C$ serial data (SDA) |
| 286 |
< |
and clock (SCL) lines, |
| 287 |
< |
a hard reset (PIA reset) line and the |
| 288 |
< |
LHC clock for each module. CCUs in the TIB can be connected to 3 or 6 modules\footnote{Actually |
| 289 |
< |
to 3 single-sided or double-sided modules, but to the Control System point of view a |
| 290 |
< |
double-sided module is seen as a pair of independent modules.} while for TID are connected to |
| 291 |
< |
6 modules (3 double-side modules) for R1 and R2 and to 5 modules for R3. |
| 292 |
< |
|
| 293 |
< |
\begin{figure} |
| 294 |
< |
\begin{center} |
| 295 |
< |
\includegraphics[width=0.85\textwidth]{Figs/mothercable.pdf} |
| 296 |
< |
\end{center} |
| 297 |
< |
\caption{A mother cable mounted on a shell. In the two upper boxes, the detail of the CCU |
| 298 |
< |
installed on MC and the connectors at the edge of the MC.} |
| 299 |
< |
\label{fig:fotomc} |
| 300 |
< |
\end{figure} |
| 301 |
< |
Moreover this cable is used to power the modules (1.25~V, 2.5~V, high voltage bias line and |
| 302 |
< |
common return).\\ |
| 303 |
< |
The mother cable receives LV and HV power for the modules, power and signals for the CCU, via three sockets located at the edge; then hosts a socket to hold and feed the CCU module and serves each module with a couple |
| 304 |
< |
of connectors (LV \& $I^2C$ and HV). |
| 305 |
< |
|
| 306 |
< |
For the TIB one mother cable serves a full string, while for the TID serves a 90 degrees sector. |
| 307 |
< |
|
| 308 |
< |
|
| 309 |
< |
%%%%%%%%%% qui l'ho un po' cambiato. C.G. |
| 310 |
< |
%\subsubsection{DOH} |
| 131 |
> |
2.5 V) low voltages. Each DCU has a unique hardware identification |
| 132 |
> |
number (called \textit{DCU Hardware ID}) that can also be read through |
| 133 |
> |
the $I^2C$ interface. By means of this number each module has an |
| 134 |
> |
unique identification. |
| 135 |
> |
|
| 136 |
> |
\subsection{The Analog Opto Hybrid} |
| 137 |
> |
|
| 138 |
> |
The Analog-Opto Hybrids~\cite{ref:aoh} (AOH) performs the |
| 139 |
> |
electrical-to-optical conversion of the electrical signals of the two |
| 140 |
> |
or three APV25 pairs, depending on the module type, by means of |
| 141 |
> |
radiation tolerant lasers and components\cite{ref:laserdriver}. |
| 142 |
> |
There is one AOH |
| 143 |
> |
per module, sitting on a ledge glued on the cooling pipe very close to |
| 144 |
> |
the front-end hybrid. Multi-mode optical fibers~\cite{ref:opto} |
| 145 |
> |
transport the signal to the counting room where the FEDs~\cite{ref:fed} |
| 146 |
> |
convert back the signal to an electrical one and digitize it. |
| 147 |
> |
Each AOH has two or three two meter long pig-tail |
| 148 |
> |
optical fibres ending with an optical plug.\\ |
| 149 |
> |
The electrical signals arrive to the AOH through front-end hybrid |
| 150 |
> |
kapton cable. The AOH is powered by the same cable. |
| 151 |
> |
By means of the AOH control logic the laser working parameters GAIN |
| 152 |
> |
and BIAS can be set via $I^2C$ control registers. |
| 153 |
> |
The GAIN parameter can be used to compensate the loss of signal |
| 154 |
> |
on the optical link to the FED input. The GAIN parameter has four |
| 155 |
> |
possible values, 0, 1, 2, 3, corresponding to a nominal |
| 156 |
> |
gain value of 0.5, 0.75, 1, 1.25, respectively. |
| 157 |
> |
During normal operation, if no damage was done to the line and |
| 158 |
> |
ideal connections, it is normally set to 1. |
| 159 |
> |
The BIAS parameter regulates the current threshold for the laser |
| 160 |
> |
diodes and can be set in the range 0$\div$127. The optimal value |
| 161 |
> |
strongly depends on temperature and also on irradiation. |
| 162 |
|
|
| 163 |
< |
%\subsubsection{DOHM} |
| 313 |
< |
|
| 314 |
< |
\subsubsection{Control Ring} |
| 163 |
> |
\subsection{The Control Ring} |
| 164 |
|
\label{fig:ctrlring} |
| 165 |
|
|
| 166 |
< |
{\it manca referenza } |
| 167 |
< |
|
| 168 |
< |
A control ring is an electro-optical circuitry that interfaces the front-end electronics to the |
| 169 |
< |
tracker control system. |
| 170 |
< |
The control ring is optically driven by a FEC (Front-End Controller) module~\cite{ref:opto} |
| 171 |
< |
located outside the tracker in the experiment control room. |
| 172 |
< |
The FEC optical signals are converted into LVDS~\cite{ref:lvds} |
| 173 |
< |
electrical signals by two DOHs |
| 174 |
< |
(Digital Opto-Hybrid) that |
| 175 |
< |
send clock, trigger, and control signals to the token ring of CCUs. |
| 176 |
< |
The DOHs are physically located on a board (DOHM~\cite{ref:dohm}) that provides up to 15 ports |
| 177 |
< |
(7 on the main DOHM board plus 8 on its |
| 166 |
> |
The control of the modules front-end electronic is implemented by means of a |
| 167 |
> |
hierarchical structure organized in groups of modules~\cite{ref:dohm}. Each group is |
| 168 |
> |
controlled by a Communication and Control Unit (CCU) taht represents a |
| 169 |
> |
``node'' in a ``token-ring'' formed by several daisy-chained CCUs and |
| 170 |
> |
known as {\it control ring}. The control ring is mastered by a Front End |
| 171 |
> |
Controller, FEC~\cite{ref:opto}, located outside the experiment by |
| 172 |
> |
means of optical signals. The entire TIB and TID contains a total of 110 |
| 173 |
> |
Control Rings. |
| 174 |
> |
|
| 175 |
> |
\begin{description} |
| 176 |
> |
\item[Digital Opto Hybrid Module] The FEC optical signals are converted into electrical signals by two DOHs |
| 177 |
> |
(Digital Opto-Hybrid) that send clock, trigger, and control signals to |
| 178 |
> |
the token ring of CCUs. The DOHs are physically located on a board, |
| 179 |
> |
Digital Opto Hybrid Module~\cite{ref:dohm} (DOHM), that provides up to |
| 180 |
> |
15 ports (7 on the main DOHM board plus 8 on its |
| 181 |
|
secondary extension or AUX) to implement the token ring. Each port |
| 182 |
< |
connects the DOHM or the AUX to a CCU located on the Mother Cable head via a 26 poles flat cable. |
| 183 |
< |
Since the failure of a single node on a token-ring structure may |
| 184 |
< |
affect the functionality of all the devices connected to the ring, a |
| 185 |
< |
redundant architecture has been implemented for the connections. In Fig.~\ref{fig:redundancy} |
| 186 |
< |
the structure of the |
| 187 |
< |
redundancy circuit is shown. Each CCU is connected to the two nearby CCUs through the primary |
| 188 |
< |
circuit (``A'' in Fig.~\ref{fig:redundancy}) and to the second next CCUs through the secondary |
| 189 |
< |
circuit (``B''). |
| 190 |
< |
In order to handle the special case of a failure either in the last CCU or in the DOH A, |
| 191 |
< |
a ``dummy CCU'' is placed on the DOHM board. |
| 192 |
< |
As shown in Fig.~\ref{fig:redundancy}, a failing CCU can thus easily bypassed using the |
| 193 |
< |
secondary circuit. |
| 182 |
> |
connects the DOHM to a CCU located on the Mother Cable head |
| 183 |
> |
via a 26 poles flat cable. |
| 184 |
> |
To cope with possible CCU failures that would affect the entire ring, the |
| 185 |
> |
control ring features the so called {\it redundancy} by means of |
| 186 |
> |
a {\it double path} layout, shown in Fig.~\ref{fig:redundancy}. |
| 187 |
> |
This design exploits the |
| 188 |
> |
two input/output replicas of the CCUs: each CCU is connected to the |
| 189 |
> |
two nearby CCUs through the primary circuit (``A'') and to the second |
| 190 |
> |
next CCUs through the secondary circuit (``B'') by which a failing CCU |
| 191 |
> |
can be bypassed. To cope with the failure either of the last |
| 192 |
> |
CCU or of the primary DOH (A), the DOHM holds a ``dummy CCU'' and a |
| 193 |
> |
spare DOH (B). |
| 194 |
|
\begin{figure} |
| 195 |
|
\begin{center} |
| 196 |
|
\includegraphics[width=0.85\textwidth]{Figs/default_redundancy.pdf} |
| 198 |
|
\caption{Scheme of primary and secondary circuit of the ring. } |
| 199 |
|
\label{fig:redundancy} |
| 200 |
|
\end{figure} |
| 201 |
< |
If no CCU is connected to a given DOHM port, a special plug must be inserted in order to ensure the |
| 202 |
< |
continuity of the primary and secondary control circuits. The redundancy properties of the system |
| 203 |
< |
are preserved by observing two ``rules'', i.e. a) if an even number of plugs is needed, |
| 204 |
< |
plugs must be organized in pairs, each pair having the two plugs inserted in consecutive ports, b) |
| 205 |
< |
if an odd number of plugs is needed, one plug must be placed in the last DOHM port |
| 206 |
< |
(before the dummy CCU), and the remaining ones following the previous rule. |
| 207 |
< |
|
| 208 |
< |
|
| 201 |
> |
If no CCU is connected to a given DOHM port, a special loop-back plug |
| 202 |
> |
must be inserted in order to ensure the continuity of the primary |
| 203 |
> |
and secondary control circuits. |
| 204 |
> |
%The redundancy properties of the system |
| 205 |
> |
%are preserved by observing two ``rules'', i.e. a) if an even number of plugs is needed, |
| 206 |
> |
%plugs must be organized in pairs, each pair having the two plugs inserted in consecutive ports, b) |
| 207 |
> |
%if an odd number of plugs is needed, one plug must be placed in the last DOHM port |
| 208 |
> |
%(before the dummy CCU), and the remaining ones following the previous rule. |
| 209 |
> |
\item[CCU] The CCU serves a group of modules and performs the following tasks: |
| 210 |
> |
distributes the clock/trigger and the hard reset to the modules; |
| 211 |
> |
dispatches the instructions received from the |
| 212 |
> |
FEC to the modules APV25s and the other ASICS via $I^2C$ or |
| 213 |
> |
vice-versa, i.e. addresses the readings from the $I^2C$ devices to the FEC. |
| 214 |
> |
Each CCU device sits on a CCU-Module (or CCUM) which carries also |
| 215 |
> |
buffering chips and a DCU. Each CCU has an hardware address |
| 216 |
> |
configurable by means of appropriate solder pads on the CCUM board to |
| 217 |
> |
be shorted or not by a SMD pull up resistor. |
| 218 |
> |
%either directed to themselves or to the devices connected to them. The first case is used |
| 219 |
> |
%for example to read the Status Register of the CCU or to raise its output PIA reset lines. |
| 220 |
> |
%While in the latter case |
| 221 |
> |
%commands are translated to the $I^2C$ protocol and forwarded to the |
| 222 |
> |
%other devices located on the sensor modules or AOH; in case of |
| 223 |
> |
%a reply from the $I^2C$ device, the reverse process is done by the CCU, which addresses the |
| 224 |
> |
%information to the FEC. |
| 225 |
> |
\end{description} |
| 226 |
> |
|
| 227 |
> |
\subsection{The Mother Cable} |
| 228 |
> |
The electrical connections between a group of modules served by the |
| 229 |
> |
same CCU are done by the {\it Mother Cable}~\cite{ref:mc}, a |
| 230 |
> |
multi-layer kapton copper circuit. An example is shown in |
| 231 |
> |
Fig.~\ref{fig:fotomc}. The mother cable is mounted on the carbon fiber |
| 232 |
> |
support structure underneath the modules. |
| 233 |
> |
The mother cable holds a CCUM and distributes the $I^2C$ serial data (SDA) |
| 234 |
> |
and clock (SCL) lines, the hard reset (PIA reset) line and the |
| 235 |
> |
clock/trigger to each module. |
| 236 |
> |
The mother cable is connected to a Power Supply unit via two sockets |
| 237 |
> |
located at the edge and feeds the modules with low voltages (1.25~V, |
| 238 |
> |
2.5~V) and the high voltage. |
| 239 |
> |
|
| 240 |
> |
In the TIB the mother cable coincides |
| 241 |
> |
with the string, i.e. six modules |
| 242 |
> |
(three double sides assemblies) in L1 and L2 and three modules in L3 |
| 243 |
> |
and L4. In the TID each mother cable serves a 90-degrees sector, |
| 244 |
> |
i.e. six modules (three double-sided assemblies) in R1 and R2 and |
| 245 |
> |
five modules in R3. |
| 246 |
|
|
| 247 |
+ |
\begin{figure} |
| 248 |
+ |
\begin{center} |
| 249 |
+ |
\includegraphics[width=0.85\textwidth]{Figs/mothercable.pdf} |
| 250 |
+ |
\end{center} |
| 251 |
+ |
\caption{A TIB mother cable with module connectors and CCU (top); |
| 252 |
+ |
details of the CCU and the connectors at the edge of the MC |
| 253 |
+ |
(middle); three module assembled string (bottom).} |
| 254 |
+ |
\label{fig:fotomc} |
| 255 |
+ |
\end{figure} |
| 256 |
|
|
| 359 |
– |
%%%%%%%%%%%%%%% fine C.G. |
