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\section{The Silicon Strip Tracker Components} |
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\section{The TIB/TID Components} |
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\label{sec:Components} |
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In this section the main SST components, with special attention |
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to the TIB ones, will be described. Detailed description will be made for items which are |
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of particular importance for the integration activities, both for assemblies and tests. |
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|
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\subsection{TIB Mechanics and Cooling} |
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|
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The TIB support structure was designed structured as 4 concentric layers |
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and realized using mainly carbon fiber. Each of these layers |
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is made up of four half-cylinder (called "shells") |
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being splitted vertically at $z=0$ and horizontally at $y=0$.\\ |
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The shell includes all the services: it has a network of cooling pipes covering both its |
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external and its internal surface. Aluminium circuits are bent into loops and soldered |
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to inlet/outlet manifolds near the shell front flange, |
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which connect several loops together. The thermal connection |
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between pipes and detector modules is made with Aluminium ledges which are |
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precisely glued |
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on the carbon fiber support structure and in good thermal contact with the pipes. |
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On each ledge there are two threaded M1 holes onto which the modules are tightened. |
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Precisely drilled slots, coaxial with the threaded holes, are the reference point where |
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insets are stick in providing mechanical reference for modules (see Fig.~\ref{fig:module_cooling}). |
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\begin{figure} |
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\centering |
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\includegraphics[width=\textwidth]{Figs/module_cooling.pdf} |
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\caption{TIB cooling. |
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\textbf{Upper picture:} a whole cooling loop with six ledges to hold three modules and three |
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smaller ledges to hold Analog Opto-Hybrids (two more cooling loops are partially visible). |
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\textbf{Lower picture:} a detail of a cooling loop. The cooling fluid direction |
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is evidenced with blue arrows, and the precision insets for module insertion are circled in |
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red. A module mounted on the nearby position is also visible.} |
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\label{fig:module_cooling} |
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\end{figure} |
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|
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Each cooling loop hosts three modules placed in a straight row, which is called a \textit{string}. |
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%A string of modules is connected to the same CCU, thus forming a control branch. |
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\subsection{The Silicon Module} |
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\subsection{The Detector Module} |
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The detector module design has been kept as simple as possible to ease their |
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mass production and integration. The silicon sensor~\cite{ref:mask}\cite{ref:sensors} |
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is glued on a carbon fibre support |
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frame which also holds the front-end electronics hybrid. The sensor is alligned, during its |
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gluing, using a reference system made by the frame aluminum insets. Since the insets are the |
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reference points to mount the module on the shell, this choice guarantee the best reproducibility |
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of the sensor position in the global shell coordinate system.\\ |
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The readout chip |
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pitch (44$\mu$m) is matched to the sensor pitch via an aluminum deposited glass substrate |
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fanout circuit (pitch |
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adapter). The hybrid circuit, which houses the front-end chips and ancillary |
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electronics, is realized using kapton multilayer technology integrating the power and |
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signal cables. \\ |
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Figure \ref{fig:moduless} and \ref{fig:moduleds} show a TIB single and double-sided module |
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respectively. |
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|
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\begin{figure}[!htb] |
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\begin{center} |
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\includegraphics[width=0.60\textwidth]{Figs/moduless.pdf} |
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\end{center} |
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\caption{A 4 chips TIB single sided module mounted on its transportation carrier.} |
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\label{fig:moduless} % Give a unique label |
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\end{figure} |
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The TIB and TID module consist of a carbon fiber support |
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frame that holds a single silicon |
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sensor~\cite{ref:mask}\cite{ref:sensors} and the front-end electronics |
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hybrid circuit. The sensor is aligned with respect to the same frame |
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aluminum insets that are used to fix the module the ledges in such a |
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way the sensor positioning is guaranteed with respect to the support |
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structure.\\ |
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|
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The double-sided TIB layers and TID rings are equipped with module |
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sandwiches capable of a space point measurement and obtained by |
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coupling back-to-back a $r\phi$ module and a special ``stereo'' |
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module with the sensor tilted by $100\mrad$. |
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|
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%The stereo module just |
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%differ from the $r\phi$ one in the details needed to cope with the |
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%different sensor orientation. |
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|
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{\bf FIX ME: descrizione/tabella dei vari tipi di moduli.} |
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|
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%The readout chip |
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%pitch (44$\mu$m) is matched to the sensor pitch via an aluminum deposited glass substrate |
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%fanout circuit (pitch |
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%adapter). The hybrid circuit, which houses the front-end chips and ancillary |
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%electronics, is realized using kapton multilayer technology integrating the power and |
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%signal cables. \\ |
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|
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A single sided module of the TID ring 1 module shown in |
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Fig.~\ref{fig:moduletid}. A TIB double-sided module is shown in Fig.~\ref{fig:moduleds} |
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|
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%\begin{figure}[!htb] |
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%\begin{center} |
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% \includegraphics[width=0.60\textwidth]{Figs/moduless.pdf} |
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%\end{center} |
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%\caption{A 4 chips TIB single sided module mounted on its transportation carrier.} |
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%\label{fig:moduless} % Give a unique label |
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%\end{figure} |
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|
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\begin{figure}[!htb] |
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\begin{center} |
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\includegraphics[width=0.60\textwidth]{Figs/moduleds.pdf} |
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\includegraphics[width=0.3\textwidth, height=0.45\textwidth,angle=90]{Figs/module-R1.pdf} |
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\hskip 5mm |
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\includegraphics[height=0.3\textwidth, width=0.45\textwidth]{Figs/moduleds.pdf} |
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\end{center} |
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\caption{A TIB double-sided module. The "stereo" module is visible reflect by a mirror.} |
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\caption{A ring 1 TID module (left panel). A TIB double-sided module, |
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the ``stereo'' module is visible reflected by a mirror (rigth panel).} |
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\label{fig:moduleds} % Give a unique label |
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\label{fig:moduletid} |
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\end{figure} |
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|
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Detectors of the TIB, TID, and of the four innermost rings of the TEC have |
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strip lengths of approximately 12 cm and pitches between 80 $\mu$m and 120 $\mu$m. |
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These detectors are made of a single sensor 320 $\mu$m thick. In the outer part |
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of the tracker (TOB and three outermost TEC rings) strip length and pitch |
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are increased by about a factor of two with respect to the inner ones. In order |
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to compensate for the noise increase due to the higher inter-strip capacitance |
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(longer strips), a silicon thickness of 500 $\mu$m has been chosen for these larger |
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detectors. \\ |
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All Silicon Strip Sensors are of single sided type and produced from $<100>$ |
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Float-zone type 6 inches wafers. |
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Double sided detectors are |
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realized simply gluing back to back two independent single sided modules: to |
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obtain a coarser but adequate resolution on the longitudinal coordinate the so |
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called “Stereo” module has the sensor tilted of 100mrad with respect to the |
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“R-Phi” one. The “Stereo” sensor and electronics are identical to the “R-Phi” |
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ones, the only difference being in the support mechanics and pitch adapters. |
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To reduce problems due to the radiation damage of the Silicon Strip Sensors |
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the Detector modules will be cooled to a temperature which, on the Silicon Sensor, |
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will reach about -10$^\circ C$.\\ |
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|
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\subsection{The Front-end Electronics} |
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The signals coming from each strip are processed by front-end readout chips |
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(APV25) mounted on the multilayer kapton hybrid circuit. The APV25~\cite{ref:apv} |
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%\subsection{The Front-end Electronics} |
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The multilayer kapton hybrid circuit holds the near front-end |
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electronics consisting of four main components: the readout chips, |
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APV25 and three ASICs (the Multiplexer, the PLL and the DCU). All |
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devices are addressed and controlled by a I$^2$C serial bus.\\ |
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The signals coming from each strip are processed by four or six front-end readout chips |
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(APV25), connected to the silicon sensor strips by means of a glass |
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substrate pitch-adapter. The APV25~\cite{ref:apv} |
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is a 128 channel chip built in radiation hard 0.25 $\mu$m |
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CMOS technology~\cite{ref:radtol}. Each channel |
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consists of a preamplifier coupled to a shaping amplifier which produces a 50ns |
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CR-RC pulse shape. The shaper output of each channel is sampled at 40MHz into |
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a 192 cell deep pipeline. The pipeline depth allows a programmable |
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level 1 trigger latency of up to 4$\mu$s, with 32 locations reserved for buffering |
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events awaiting readout. Each pipeline channel is read out by an analogue |
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circuitry which can operate in one of two modes. In {\it peak mode} only one |
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sample per channel is read (timed to be at the peak of the analogue pulse |
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shape). In {\it deconvolution mode} |
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\cite{ref:deconvolution} three samples are sequentially read and |
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the output is a weighted sum of all three. The deconvolution operation results |
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in a re-shaping of the analogue pulse shape to one that peaks at 25 ns and |
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returns rapidly to the baseline. This operating mode is particularly important |
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for correct bunch crossing identification (i.e. off-time interactions suppression) |
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during the high luminosity running |
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phase of the LHC. A unity gain inverter, which helps in reducing the common mode |
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noise contribution, is included between the preamp and |
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shaper and can be switched in or out. |
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On receiving a positive level 1 trigger decision the APV25 sends out serially, |
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at 20MHz rate, the 128 analogue signals together with information about the |
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pipeline address and the chip error status; signals coming from two APV25 are |
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interlaced together on a differential line by a Multiplexer chip~\cite{ref:mux} |
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which is located |
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on the hybrid circuit too. |
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Since the chip may not output data for a considerable time when it is waiting for a trigger, |
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it is necessary for the DAQ electronics to remain synchronised with the APV25 |
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when it eventually begins to read out data. To allow for this |
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the chip outputs a synchronisation pulse, of 25ns duration, called a 'tick mark' every |
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70 clock cycles when there is no data to read out. |
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The APV25 electrical signals are then converted to optical |
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ones in dedicated Analog-Opto Hybrids (AOH\cite{ref:aoh}) few centimeters away from |
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the detector, and transmitted to the counting room by means of multi-mode |
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optical fibres~\cite{ref:opto}, where they are digitized~\cite{ref:fed}. |
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The LHC 40MHz clock, which |
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drives the APV25 sampling can be delayed at the single module level by |
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means of a PLL (phase lock loop) chip\cite{ref:pll} to take into account the |
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different cable lengths and distances from the interaction point. \\ |
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The Detector Control Unit (DCU) is a rad-hard ASIC, mounted on the |
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front-end hybrid. This chip |
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contains an eight channel analog to digital converter, |
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CMOS technology~\cite{ref:radtol}. Each channel consists of a |
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preamplifier coupled to a CR-RC 50ns shaper. The shaper output is sampled at 40MHz into |
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a 192 cells pipeline that allows trigger latencies up to 4$\mu$s.\\ |
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The APV25 can operate in {\it peak mode} or in {\it deconvolution |
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mode}. In the former the shaping time is $50\ns$; in the latter, by |
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using a deconvolution filter~\cite{ref:deconvolution}, the |
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effective shaping time is 25ns. In addition, there is also the |
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possibility to switch on (Inv) or off an inverter to fully exploit |
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the dynamic range of the preamplifier with signals of both |
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polarity. Standard operation mode for Silicon Sensor is with |
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inverter on. |
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{\bf FIX ME: ma serve??? Nel seguito non si fa mai menzione dei vari |
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modi di funzionamento dell'APV - forse da aggiungere nela |
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descrizione del ped-noi run?} |
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|
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On receiving a level 1 trigger the APV25 sends out serially |
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%, at 20MHz rate, |
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the 128 analogue signals together with information about the |
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pipeline address and the chip error status; two APV25 are multiplexed |
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on a differential line by the Multiplexer chip~\cite{ref:mux}. |
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In absence of data to stream out, for synchronization purposes, the |
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APV issues a 25ns pulse called ``tick mark'' |
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with a period of 70 clock cycles.\\ |
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The PLL chip\cite{ref:pll} allows the clock to be delayed to |
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compensate for path differences of control signals and for any |
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electronics delay. The PLL also decodes the trigger signals that are |
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encoded on the clock line.\\ |
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The Detector Control Unit (DCU) contains an eight-channel ADC, |
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two constant current sources and a temperature sensor. It |
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monitors two sets of thermistors, one on the sensor |
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and one on the hybrid, its own internal temperature, the |
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silicon detector bias current and the two (1.25 V and |
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2.5 V) low voltages.\\ |
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Each DCU has a unique hardware identification |
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number (called \textit{DCU Hardware ID}) that can also be read through the $I^2C$ interface. |
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This number can be used to identify each module and |
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to act as a link between the construction database, that |
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stores the module information, |
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and the online databases, storing information during data taking. |
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|
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\subsection{The off-detector Electronics} |
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\subsubsection{AOH} |
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|
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The electric to optical conversion is done by radiation hard lasers~\cite{Gill:2005ui}. |
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These devices sit on a dedicated board, called Analog Opto-Hybrid, which is |
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fixed on a ledge glued on the cooling pipe very close to the detector module. |
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The electrical signals arrive to the AOH through the module front-end hybrid |
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kapton cable tail which carries the AOH power lines too. |
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The AOH can hold up to three lasers (only two are mounted for single sided 4 APV chips |
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modules) and their control hardware.\\ |
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The on-board control logic is used to drive the lasers: it has an $I^2C$ |
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control register for each laser |
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which is split in a 2-bit section (GAIN: 0$\div$3) and a 7-bit section (BIAS: 0$\div$127). |
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The GAIN value can be used to compensate the loss of signal on the fibre link |
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and optical connections from AOHs to FEDs. |
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During normal operation, if no damage was done to the line and ideal connections, |
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it is normally set to 1. The actual gain |
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of the AOH is not proportional to the GAIN parameter, as the four |
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possible nominal gains are: 0.5, 0.75, 1, 1.25 (normalised w.r.t. GAIN=3). |
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The BIAS parameter regulates the current threshold for the laser diodes. |
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Its optimal value strongly depends on temperature and also on irradiation. |
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|
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\subsubsection{CCU} |
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|
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The Silicon Strip Tracker Detector Modules are controlled by a set of signals |
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(clock, trigger, $I^2C$ lines) which are dispatched to them via a |
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token ring strucured circuitry ("control ring"). |
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CCUs are the nodes of this structure. They receive instructions from the external |
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FEC (front-End Controller) |
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either directed to themselves or to the $I^2C$ devices connected to them. The first case is used |
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for example to read the Status Register of the CCU or to raise its output PIA reset lines. |
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While in the latter case |
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commands are translated to the $I^2C$ protocol and forwarded to the |
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other devices located on the detector modules or AOH; in case of |
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a reply from the $I^2C$ device, the reverse process is done by the CCU, which addresses the |
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information to the FEC. |
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The CCU device sits on a CCU-Module (or CCUM) which carries also buffering chips and a DCU. |
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|
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|
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\subsubsection{Mother Cable} |
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|
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In the TIB a multi-layer kapton copper cable ("Mother Cable", see Fig.~\ref{fig:fotomc}) |
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is mounted on the carbon fiber shell underneath the |
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modules. It carries the $I^2C$ serial data (SDA) |
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and clock (SCL) lines, |
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a hard reset (PIA reset) line and the |
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LHC clock for each module. CCUs in the TIB can be connected to 3 or 6 modules\footnote{Actually |
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to 3 single-sided or double-sided modules, but to the Control System point of view a |
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double-sided module is seen as a pair of independent modules.}. |
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|
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\begin{figure} |
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\begin{center} |
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\includegraphics[width=0.85\textwidth]{Figs/mothercable.pdf} |
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\end{center} |
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\caption{A mother cable mounted on a shell. In the two upper boxes, the detail of the CCU |
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installed on MC and the connectors at the edge of the MC.} |
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\label{fig:fotomc} |
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\end{figure} |
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Moreover this cable is used to power the modules (1.25~V, 2.5~V, high voltage bias line and |
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common return).\\ |
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The mother cable hosts a socket to hold the CCU module, three connectors |
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for the low voltage lines, HV lines and the token ring cable. Each module is served by a couple |
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of connectors (LV \& $I^2C$ and HV). A CCU and the modules connected to the |
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same mother cable are called a \textit{string}. |
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|
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%%%%%%%%%% qui l'ho un po' cambiato. C.G. |
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%\subsubsection{DOH} |
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|
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%\subsubsection{DOHM} |
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silicon sensor bias current and the two (1.25 V and |
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2.5 V) low voltages. Each DCU has a unique hardware identification |
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number (called \textit{DCU Hardware ID}) that can also be read through |
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the $I^2C$ interface. By means of this number each module has an |
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unique identification. |
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|
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\subsection{The Analog Opto Hybrid} |
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|
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The Analog-Opto Hybrids~\cite{ref:aoh} (AOH) performs the |
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electrical-to-optical conversion of the electrical signals of the two |
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or three APV25 pairs, depending on the module type, by means of |
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radiation hard lasers~\cite{Gill:2005ui}. There is one AOH |
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per module, sitting on a ledge glued on the cooling pipe very close to |
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the silicon module hybrid. Multi-mode optical fiber~\cite{ref:opto} |
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transport the signal to the FEDs~\cite{ref:fed} for the |
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digitization. Each AOH has two or three two meter long pig-tail |
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optical fibres ending with an optical plug.\\ |
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The electrical signals arrive to the AOH through hybrid |
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kapton cable. The AOH is powered by the same cable. |
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By means of the AOH control logic the laser working parameters GAIN |
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and BIAS can be set via $I^2C$ control registers. |
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The GAIN parameter can be used to compensate the loss of signal |
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on the optical link to the FED input. The GAIN parameter has four |
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possible values, 0, 1, 2, 3, corresponding to a nominal |
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gain value of 0.5, 0.75, 1, 1.25, respectively, normalized at |
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GAIN=3. During normal operation, if no damage was done to the line and |
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ideal connections, it is normally set to 1. |
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The BIAS parameter regulates the current threshold for the laser |
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diodes and can be set in the range 0$\div$127. The optimal value |
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strongly depends on temperature and also on irradiation. |
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|
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\subsubsection{Control Ring} |
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\subsection{The Control Ring} |
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\label{fig:ctrlring} |
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A control ring is an electro-optical circuitry that interfaces the detector to the |
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tracker control system. |
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The control ring is optically driven by a FEC (Front-End Controller) module~\cite{ref:opto} |
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located outside the tracker in the experiment control room. |
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The FEC optical signals are converted into LVDS~\cite{ref:lvds} |
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electrical signals by two DOHs |
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(Digital Opto-Hybrid) that |
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send clock, trigger, and control signals to the token ring of CCUs. |
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The DOHs are physically located on a board (DOHM) that provides up to 15 ports |
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(7 on the main DOHM board plus 8 on its |
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|
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The control of the modules front-end electronic is implemented by means of a |
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hierarchical structure organized in groups of modules~\cite{ref:dohm}. Each group is |
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controlled by a Communication and Control Unit (CCU) taht represents a |
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``node'' in a ``token-ring'' formed by several daisy-chained CCUs and |
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known as {\it control ring}. The control ring is mastered by a Front End |
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Controller, FEC~\cite{ref:opto}, located outside the experiment by |
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means of optical signals. The entire TIB and TID contains roughly 100 |
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Control Rings. |
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|
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\begin{description} |
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\item[Digital Opto Hybrid Module] The FEC optical signals are converted into electrical signals by two DOHs |
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(Digital Opto-Hybrid) that send clock, trigger, and control signals to |
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the token ring of CCUs. The DOHs are physically located on a board, |
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Digital Opto Hybrid Module~\cite{ref:dohm} (DOHM), that provides up to |
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15 ports (7 on the main DOHM board plus 8 on its |
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|
secondary extension or AUX) to implement the token ring. Each port |
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connects the DOHM or the AUX to a CCU located on the Mother Cable head via a 26 poles flat cable. |
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Since the failure of a single node on a token-ring structure may |
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affect the functionality of all the devices connected to the ring, a |
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redundant architecture has been implemented for the connections. In Fig.~\ref{fig:redundancy} |
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the structure of the |
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redundancy circuit is shown. Each CCU is connected to the two nearby CCUs through the primary |
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circuit (``A'' in Fig.~\ref{fig:redundancy}) and to the second next CCUs through the secondary |
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circuit (``B''). |
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In order to handle the special case of a failure either in the last CCU or in the DOH A, |
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a ``dummy CCU'' is placed on the DOHM board. |
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As shown in Fig.~\ref{fig:redundancy}, a failing CCU can thus easily bypassed using the |
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secondary circuit. |
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connects the DOHM to a CCU located on the Mother Cable head |
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via a 26 poles flat cable. |
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To cope with possible CCU failures that would affect the entire ring, the |
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control ring features the so called {\it redundancy} by means of |
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a clever layout, shown in Fig.~\ref{fig:redundancy}, that exploits the |
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two input/output replicas of the CCUs: each CCU is connected to the |
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two nearby CCUs through the primary circuit (``A'') and to the second |
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next CCUs through the secondary circuit (``B'') by which a failing CCU |
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can be bypassed. To cope with the failure either of the last |
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CCU or of the primary DOH (A), the DOHM holds a ``dummy CCU'' and a |
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spare DOH (B). |
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\begin{figure} |
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\begin{center} |
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\includegraphics[width=0.85\textwidth]{Figs/default_redundancy.pdf} |
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\caption{Scheme of primary and secondary circuit of the ring. } |
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\label{fig:redundancy} |
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|
\end{figure} |
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If no CCU is connected to a given DOHM port, a special plug must be inserted in order to ensure the |
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continuity of the primary and secondary control circuits. The redundancy properties of the system |
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are preserved by observing two ``rules'', i.e. a) if an even number of plugs is needed, |
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plugs must be organized in pairs, each pair having the two plugs inserted in consecutive ports, b) |
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if an odd number of plugs is needed, one plug must be placed in the last DOHM port |
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(before the dummy CCU), and the remaining ones following the previous rule. |
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|
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|
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If no CCU is connected to a given DOHM port, a special loop-back plug |
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must be inserted in order to ensure the continuity of the primary |
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and secondary control circuits. |
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%The redundancy properties of the system |
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%are preserved by observing two ``rules'', i.e. a) if an even number of plugs is needed, |
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%plugs must be organized in pairs, each pair having the two plugs inserted in consecutive ports, b) |
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%if an odd number of plugs is needed, one plug must be placed in the last DOHM port |
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%(before the dummy CCU), and the remaining ones following the previous rule. |
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\item[CCU] The CCU serves a group of modules and performs the following tasks: |
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distributes the clock/trigger and the hard reset to the modules; |
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dispatches the instructions received from the |
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FEC to the modules APV25s and the other ASICS via $I^2C$ or |
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vice-versa, i.e. addresses the readings from the $I^2C$ devices to the FEC. |
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Each CCU device sits on a CCU-Module (or CCUM) which carries also |
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buffering chips and a DCU. Each CCU has an hardware address |
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configurable by means of appropriate solder pads on the CCUM board to |
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be shorted or not by a SMD pull up resistor. |
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%either directed to themselves or to the devices connected to them. The first case is used |
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%for example to read the Status Register of the CCU or to raise its output PIA reset lines. |
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%While in the latter case |
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%commands are translated to the $I^2C$ protocol and forwarded to the |
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%other devices located on the sensor modules or AOH; in case of |
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%a reply from the $I^2C$ device, the reverse process is done by the CCU, which addresses the |
| 186 |
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%information to the FEC. |
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\end{description} |
| 188 |
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|
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\subsection{The Mother Cable} |
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The electrical connections between a group of modules served by the |
| 191 |
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same CCU are done by the {\it Mother Cable}~\cite{ref:mc}, a flexible |
| 192 |
> |
multi-layer kapton copper circuit. An example is shown in |
| 193 |
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Fig.~\ref{fig:fotomc}. The mother cable is mounted on the carbon fiber |
| 194 |
> |
support structure underneath the modules. |
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The mother cable holds a CCUM and distributes the $I^2C$ serial data (SDA) |
| 196 |
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and clock (SCL) lines, the hard reset (PIA reset) line and the |
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clock/trigger to each module. |
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The mother cable is connected to a Power Supply unit via two sockets |
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located at the edge and feeds the modules with low voltages (1.25~V, |
| 200 |
> |
2.5~V) and the high voltage. |
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|
| 202 |
> |
In the TIB the mother cable coincides |
| 203 |
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with the string, i.e. six modules |
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(three double sides assemblies) in L1 and L2 and three modules in L3 |
| 205 |
> |
and L4. In the TID each mother cable serves a 90-degrees sector, |
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i.e. six modules (three double-sided assemblies) in R1 and R2 and |
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five modules in R3. |
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|
|
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\begin{figure} |
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\begin{center} |
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\includegraphics[width=0.85\textwidth]{Figs/mothercable.pdf} |
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\end{center} |
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\caption{A mother cable mounted on a shell. In the two upper boxes, the detail of the CCU |
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installed on MC and the connectors at the edge of the MC.} |
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\label{fig:fotomc} |
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\end{figure} |
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|
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%%%%%%%%%%%%%%% fine C.G. |
