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root/cvsroot/UserCode/TIBTIDNotes/TIBTIDIntNote/SiStripComponents.tex
Revision: 1.4
Committed: Mon Mar 9 15:41:05 2009 UTC (16 years, 1 month ago) by sguazz
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Text revision, some figures added, some removed

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# Content
1 \section{The TIB/TID Components}
2 \label{sec:Components}
3
4 \subsection{The Silicon Module}
5
6 The TIB and TID module consist of a carbon fiber support
7 frame that holds a single silicon
8 sensor~\cite{ref:mask}\cite{ref:sensors} and the front-end electronics
9 hybrid circuit. The sensor is aligned with respect to the same frame
10 aluminum insets that are used to fix the module the ledges in such a
11 way the sensor positioning is guaranteed with respect to the support
12 structure.\\
13
14 The double-sided TIB layers and TID rings are equipped with module
15 sandwiches capable of a space point measurement and obtained by
16 coupling back-to-back a $r\phi$ module and a special ``stereo''
17 module with the sensor tilted by $100\mrad$.
18
19 %The stereo module just
20 %differ from the $r\phi$ one in the details needed to cope with the
21 %different sensor orientation.
22
23 {\bf FIX ME: descrizione/tabella dei vari tipi di moduli.}
24
25 %The readout chip
26 %pitch (44$\mu$m) is matched to the sensor pitch via an aluminum deposited glass substrate
27 %fanout circuit (pitch
28 %adapter). The hybrid circuit, which houses the front-end chips and ancillary
29 %electronics, is realized using kapton multilayer technology integrating the power and
30 %signal cables. \\
31
32 A single sided module of the TID ring 1 module shown in
33 Fig.~\ref{fig:moduletid}. A TIB double-sided module is shown in Fig.~\ref{fig:moduleds}
34
35 %\begin{figure}[!htb]
36 %\begin{center}
37 % \includegraphics[width=0.60\textwidth]{Figs/moduless.pdf}
38 %\end{center}
39 %\caption{A 4 chips TIB single sided module mounted on its transportation carrier.}
40 %\label{fig:moduless} % Give a unique label
41 %\end{figure}
42
43 \begin{figure}[!htb]
44 \begin{center}
45 \includegraphics[width=0.3\textwidth, height=0.45\textwidth,angle=90]{Figs/module-R1.pdf}
46 \hskip 5mm
47 \includegraphics[height=0.3\textwidth, width=0.45\textwidth]{Figs/moduleds.pdf}
48 \end{center}
49 \caption{A ring 1 TID module (left panel). A TIB double-sided module,
50 the ``stereo'' module is visible reflected by a mirror (rigth panel).}
51 \label{fig:moduleds} % Give a unique label
52 \label{fig:moduletid}
53 \end{figure}
54
55 %\subsection{The Front-end Electronics}
56 The multilayer kapton hybrid circuit holds the near front-end
57 electronics consisting of four main components: the readout chips,
58 APV25 and three ASICs (the Multiplexer, the PLL and the DCU). All
59 devices are addressed and controlled by a I$^2$C serial bus.\\
60 The signals coming from each strip are processed by four or six front-end readout chips
61 (APV25), connected to the silicon sensor strips by means of a glass
62 substrate pitch-adapter. The APV25~\cite{ref:apv}
63 is a 128 channel chip built in radiation hard 0.25 $\mu$m
64 CMOS technology~\cite{ref:radtol}. Each channel consists of a
65 preamplifier coupled to a CR-RC 50ns shaper. The shaper output is sampled at 40MHz into
66 a 192 cells pipeline that allows trigger latencies up to 4$\mu$s.\\
67 The APV25 can operate in {\it peak mode} or in {\it deconvolution
68 mode}. In the former the shaping time is $50\ns$; in the latter, by
69 using a deconvolution filter~\cite{ref:deconvolution}, the
70 effective shaping time is 25ns. In addition, there is also the
71 possibility to switch on (Inv) or off an inverter to fully exploit
72 the dynamic range of the preamplifier with signals of both
73 polarity. Standard operation mode for Silicon Sensor is with
74 inverter on.
75 {\bf FIX ME: ma serve??? Nel seguito non si fa mai menzione dei vari
76 modi di funzionamento dell'APV - forse da aggiungere nela
77 descrizione del ped-noi run?}
78
79 On receiving a level 1 trigger the APV25 sends out serially
80 %, at 20MHz rate,
81 the 128 analogue signals together with information about the
82 pipeline address and the chip error status; two APV25 are multiplexed
83 on a differential line by the Multiplexer chip~\cite{ref:mux}.
84 In absence of data to stream out, for synchronization purposes, the
85 APV issues a 25ns pulse called ``tick mark''
86 with a period of 70 clock cycles.\\
87 The PLL chip\cite{ref:pll} allows the clock to be delayed to
88 compensate for path differences of control signals and for any
89 electronics delay. The PLL also decodes the trigger signals that are
90 encoded on the clock line.\\
91 The Detector Control Unit (DCU) contains an eight-channel ADC,
92 two constant current sources and a temperature sensor. It
93 monitors two sets of thermistors, one on the sensor
94 and one on the hybrid, its own internal temperature, the
95 silicon sensor bias current and the two (1.25 V and
96 2.5 V) low voltages. Each DCU has a unique hardware identification
97 number (called \textit{DCU Hardware ID}) that can also be read through
98 the $I^2C$ interface. By means of this number each module has an
99 unique identification.
100
101 \subsection{The Analog Opto Hybrid}
102
103 The Analog-Opto Hybrids~\cite{ref:aoh} (AOH) performs the
104 electrical-to-optical conversion of the electrical signals of the two
105 or three APV25 pairs, depending on the module type, by means of
106 radiation hard lasers~\cite{Gill:2005ui}. There is one AOH
107 per module, sitting on a ledge glued on the cooling pipe very close to
108 the silicon module hybrid. Multi-mode optical fiber~\cite{ref:opto}
109 transport the signal to the FEDs~\cite{ref:fed} for the
110 digitization. Each AOH has two or three two meter long pig-tail
111 optical fibres ending with an optical plug.\\
112 The electrical signals arrive to the AOH through hybrid
113 kapton cable. The AOH is powered by the same cable.
114 By means of the AOH control logic the laser working parameters GAIN
115 and BIAS can be set via $I^2C$ control registers.
116 The GAIN parameter can be used to compensate the loss of signal
117 on the optical link to the FED input. The GAIN parameter has four
118 possible values, 0, 1, 2, 3, corresponding to a nominal
119 gain value of 0.5, 0.75, 1, 1.25, respectively, normalized at
120 GAIN=3. During normal operation, if no damage was done to the line and
121 ideal connections, it is normally set to 1.
122 The BIAS parameter regulates the current threshold for the laser
123 diodes and can be set in the range 0$\div$127. The optimal value
124 strongly depends on temperature and also on irradiation.
125
126 \subsection{The Control Ring}
127 \label{fig:ctrlring}
128
129 The control of the modules front-end electronic is implemented by means of a
130 hierarchical structure organized in groups of modules~\cite{ref:dohm}. Each group is
131 controlled by a Communication and Control Unit (CCU) taht represents a
132 ``node'' in a ``token-ring'' formed by several daisy-chained CCUs and
133 known as {\it control ring}. The control ring is mastered by a Front End
134 Controller, FEC~\cite{ref:opto}, located outside the experiment by
135 means of optical signals. The entire TIB and TID contains roughly 100
136 Control Rings.
137
138 \begin{description}
139 \item[Digital Opto Hybrid Module] The FEC optical signals are converted into electrical signals by two DOHs
140 (Digital Opto-Hybrid) that send clock, trigger, and control signals to
141 the token ring of CCUs. The DOHs are physically located on a board,
142 Digital Opto Hybrid Module~\cite{ref:dohm} (DOHM), that provides up to
143 15 ports (7 on the main DOHM board plus 8 on its
144 secondary extension or AUX) to implement the token ring. Each port
145 connects the DOHM to a CCU located on the Mother Cable head
146 via a 26 poles flat cable.
147 To cope with possible CCU failures that would affect the entire ring, the
148 control ring features the so called {\it redundancy} by means of
149 a clever layout, shown in Fig.~\ref{fig:redundancy}, that exploits the
150 two input/output replicas of the CCUs: each CCU is connected to the
151 two nearby CCUs through the primary circuit (``A'') and to the second
152 next CCUs through the secondary circuit (``B'') by which a failing CCU
153 can be bypassed. To cope with the failure either of the last
154 CCU or of the primary DOH (A), the DOHM holds a ``dummy CCU'' and a
155 spare DOH (B).
156 \begin{figure}
157 \begin{center}
158 \includegraphics[width=0.85\textwidth]{Figs/default_redundancy.pdf}
159 \end{center}
160 \caption{Scheme of primary and secondary circuit of the ring. }
161 \label{fig:redundancy}
162 \end{figure}
163 If no CCU is connected to a given DOHM port, a special loop-back plug
164 must be inserted in order to ensure the continuity of the primary
165 and secondary control circuits.
166 %The redundancy properties of the system
167 %are preserved by observing two ``rules'', i.e. a) if an even number of plugs is needed,
168 %plugs must be organized in pairs, each pair having the two plugs inserted in consecutive ports, b)
169 %if an odd number of plugs is needed, one plug must be placed in the last DOHM port
170 %(before the dummy CCU), and the remaining ones following the previous rule.
171 \item[CCU] The CCU serves a group of modules and performs the following tasks:
172 distributes the clock/trigger and the hard reset to the modules;
173 dispatches the instructions received from the
174 FEC to the modules APV25s and the other ASICS via $I^2C$ or
175 vice-versa, i.e. addresses the readings from the $I^2C$ devices to the FEC.
176 Each CCU device sits on a CCU-Module (or CCUM) which carries also
177 buffering chips and a DCU. Each CCU has an hardware address
178 configurable by means of appropriate solder pads on the CCUM board to
179 be shorted or not by a SMD pull up resistor.
180 %either directed to themselves or to the devices connected to them. The first case is used
181 %for example to read the Status Register of the CCU or to raise its output PIA reset lines.
182 %While in the latter case
183 %commands are translated to the $I^2C$ protocol and forwarded to the
184 %other devices located on the sensor modules or AOH; in case of
185 %a reply from the $I^2C$ device, the reverse process is done by the CCU, which addresses the
186 %information to the FEC.
187 \end{description}
188
189 \subsection{The Mother Cable}
190 The electrical connections between a group of modules served by the
191 same CCU are done by the {\it Mother Cable}~\cite{ref:mc}, a flexible
192 multi-layer kapton copper circuit. An example is shown in
193 Fig.~\ref{fig:fotomc}. The mother cable is mounted on the carbon fiber
194 support structure underneath the modules.
195 The mother cable holds a CCUM and distributes the $I^2C$ serial data (SDA)
196 and clock (SCL) lines, the hard reset (PIA reset) line and the
197 clock/trigger to each module.
198 The mother cable is connected to a Power Supply unit via two sockets
199 located at the edge and feeds the modules with low voltages (1.25~V,
200 2.5~V) and the high voltage.
201
202 In the TIB the mother cable coincides
203 with the string, i.e. six modules
204 (three double sides assemblies) in L1 and L2 and three modules in L3
205 and L4. In the TID each mother cable serves a 90-degrees sector,
206 i.e. six modules (three double-sided assemblies) in R1 and R2 and
207 five modules in R3.
208
209 \begin{figure}
210 \begin{center}
211 \includegraphics[width=0.85\textwidth]{Figs/mothercable.pdf}
212 \end{center}
213 \caption{A mother cable mounted on a shell. In the two upper boxes, the detail of the CCU
214 installed on MC and the connectors at the edge of the MC.}
215 \label{fig:fotomc}
216 \end{figure}
217