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\section{The TIB/TID Components} |
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\section{The Integration Components} |
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\label{sec:Components} |
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\subsection{The Silicon Module} |
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The TIB and TID module consist of a carbon fiber support |
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The TIB and TID module\ref{table:modules} consist of a carbon fiber support |
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frame that holds a single silicon |
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sensor~\cite{ref:mask}\cite{ref:sensors} and the front-end electronics |
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hybrid circuit. The sensor is aligned with respect to the same frame |
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hybrid circuit\cite{ref:hybrid}. |
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These detectors are produced from individual, 320~$\mu$m thick, sensors. |
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All silicon strip sensors are of the |
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single-sided ``p-on-n'' type |
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with integrated decoupling capacitors, aluminium readout strips |
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and polysilicon bias resistors. |
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The sensor is aligned with respect to the same frame |
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aluminum insets that are used to fix the module the ledges in such a |
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way the sensor positioning is guaranteed with respect to the support |
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structure.\\ |
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structure~\cite{ref:assembly}.\\ |
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Double-sided detectors are built by simply assembling two independent |
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single-sided modules (``R-Phi'' and ``Stereo'') back to back. |
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The double-sided TIB layers and TID rings are equipped with module |
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sandwiches capable of a space point measurement and obtained by |
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coupling back-to-back a $r\phi$ module and a special ``stereo'' |
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module with the sensor tilted by $100\mrad$. |
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The stereo sensor and electronics are identical to the R-Phi ones, the only |
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difference being in the support mechanics and pitch adapters. \\ |
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|
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|
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%The stereo module just |
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%differ from the $r\phi$ one in the details needed to cope with the |
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%different sensor orientation. |
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\begin{table}[!htb] |
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\begin{center} |
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\caption[smallcaption]{Details on the different TIB/TID modules. } |
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\label{table:modules} |
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%\begin{tabular}{|l||c|c|c|c|c|c|c|} |
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\begin{tabular}{|l|ccccc|} |
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\hline |
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Module & pitch ($\mu$m) & Assembly &Active area & \# of APVs & \# of channels \\ |
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type & & type &$cm^2$ & & per module \\ |
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\hline |
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% \hline |
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TIB Layer 1-2 $r-/phi$ & 80 & DS & 35 & 6 & 768 \\ |
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TIB Layer 1-2 stereo & 80 & DS & 35 & 6 & 768 \\ |
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TIB Layer 3-4 $r-/phi$ & 120 & SS & 35 & 4 & 512 \\ |
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TID Ring 1 $r-/phi$ & 81-119 & DS & 85 & 6 & 768 \\ |
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TID Ring 1 stereo & 81-119 & DS & 85 & 6 & 768 \\ |
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TID Ring 2 $r-/phi$ & 81-119 & DS & 88 & 6 & 768 \\ |
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TID Ring 2 stereo & 81-119 & DS & 88 & 6 & 768 \\ |
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TID Ring 3 $r-/phi$ & 123-158 & SS & 79 & 4 & 512 \\ |
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\hline |
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\end{tabular} |
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\end{center} |
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\end{table} |
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|
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{\bf FIX ME: descrizione/tabella dei vari tipi di moduli.} |
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%%{\bf FIX ME: descrizione/tabella dei vari tipi di moduli.} |
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|
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%The readout chip |
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%pitch (44$\mu$m) is matched to the sensor pitch via an aluminum deposited glass substrate |
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%electronics, is realized using kapton multilayer technology integrating the power and |
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%signal cables. \\ |
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A single sided module of the TID ring 1 module shown in |
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Fig.~\ref{fig:moduletid}. A TIB double-sided module is shown in Fig.~\ref{fig:moduleds} |
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A single sided module of the TID ring 3 and a TIB double-sided module |
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are shown in Fig.~\ref{fig:moduleds}. |
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%\begin{figure}[!htb] |
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%\begin{center} |
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\hskip 5mm |
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\includegraphics[height=0.3\textwidth, width=0.45\textwidth]{Figs/moduleds.pdf} |
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\end{center} |
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\caption{A ring 1 TID module (left panel). A TIB double-sided module, |
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\caption{A ring 3 TID module (left panel). A TIB double-sided module, |
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the ``stereo'' module is visible reflected by a mirror (rigth panel).} |
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\label{fig:moduleds} % Give a unique label |
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\label{fig:moduletid} |
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\end{figure} |
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%\subsection{The Front-end Electronics} |
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The multilayer kapton hybrid circuit holds the near front-end |
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electronics consisting of four main components: the readout chips, |
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APV25 and three ASICs (the Multiplexer, the PLL and the DCU). All |
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The multilayer kapton hybrid circuit holds the module front-end |
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electronics consisting of four main components: the readout chips |
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(APV25) and three ASICs (the Multiplexer, the PLL and the DCU). All |
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devices are addressed and controlled by a I$^2$C serial bus.\\ |
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The signals coming from each strip are processed by four or six front-end readout chips |
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(APV25), connected to the silicon sensor strips by means of a glass |
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The signals coming from each strip are processed by four or six front-end |
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readout chips, connected to the silicon sensor strips by means of a glass |
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substrate pitch-adapter. The APV25~\cite{ref:apv} |
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is a 128 channel chip built in radiation hard 0.25 $\mu$m |
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is a 128 channel chip built in radiation tolerant 0.25 $\mu$m |
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CMOS technology~\cite{ref:radtol}. Each channel consists of a |
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preamplifier coupled to a CR-RC 50ns shaper. The shaper output is sampled at 40MHz into |
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a 192 cells pipeline that allows trigger latencies up to 4$\mu$s.\\ |
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mode}. In the former the shaping time is $50\ns$; in the latter, by |
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using a deconvolution filter~\cite{ref:deconvolution}, the |
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effective shaping time is 25ns. In addition, there is also the |
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possibility to switch on (Inv) or off an inverter to fully exploit |
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the dynamic range of the preamplifier with signals of both |
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polarity. Standard operation mode for Silicon Sensor is with |
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inverter on. |
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{\bf FIX ME: ma serve??? Nel seguito non si fa mai menzione dei vari |
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modi di funzionamento dell'APV - forse da aggiungere nela |
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descrizione del ped-noi run?} |
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possibility to switch on or off an inverter stage which slightly |
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decreases the common mode noise contribution. |
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% Standard operation mode for Silicon Sensor is with |
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% inverter on. |
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%%{\bf FIX ME: ma serve??? Nel seguito non si fa mai menzione dei vari |
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%% modi di funzionamento dell'APV - forse da aggiungere nela |
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%% descrizione del ped-noi run?} |
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On receiving a level 1 trigger the APV25 sends out serially |
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%, at 20MHz rate, |
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In absence of data to stream out, for synchronization purposes, the |
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APV issues a 25ns pulse called ``tick mark'' |
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with a period of 70 clock cycles.\\ |
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The PLL chip\cite{ref:pll} allows the clock to be delayed to |
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The PLL chip\cite{ref:pll} allows the clock to be delayed by 1.04ns |
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steps, to |
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compensate for path differences of control signals and for any |
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electronics delay. The PLL also decodes the trigger signals that are |
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encoded on the clock line.\\ |
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or three APV25 pairs, depending on the module type, by means of |
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radiation hard lasers~\cite{Gill:2005ui}. There is one AOH |
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per module, sitting on a ledge glued on the cooling pipe very close to |
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the silicon module hybrid. Multi-mode optical fiber~\cite{ref:opto} |
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transport the signal to the FEDs~\cite{ref:fed} for the |
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digitization. Each AOH has two or three two meter long pig-tail |
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the front-end hybrid. Multi-mode optical fibers~\cite{ref:opto} |
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transport the signal to the counting room where the FEDs~\cite{ref:fed} |
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convert back the signal to an electrical one and digitize it. |
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Each AOH has two or three two meter long pig-tail |
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optical fibres ending with an optical plug.\\ |
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The electrical signals arrive to the AOH through hybrid |
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The electrical signals arrive to the AOH through front-end hybrid |
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kapton cable. The AOH is powered by the same cable. |
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By means of the AOH control logic the laser working parameters GAIN |
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and BIAS can be set via $I^2C$ control registers. |
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The GAIN parameter can be used to compensate the loss of signal |
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on the optical link to the FED input. The GAIN parameter has four |
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possible values, 0, 1, 2, 3, corresponding to a nominal |
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gain value of 0.5, 0.75, 1, 1.25, respectively, normalized at |
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GAIN=3. During normal operation, if no damage was done to the line and |
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gain value of 0.5, 0.75, 1, 1.25, respectively. |
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During normal operation, if no damage was done to the line and |
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ideal connections, it is normally set to 1. |
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The BIAS parameter regulates the current threshold for the laser |
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diodes and can be set in the range 0$\div$127. The optimal value |
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``node'' in a ``token-ring'' formed by several daisy-chained CCUs and |
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known as {\it control ring}. The control ring is mastered by a Front End |
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Controller, FEC~\cite{ref:opto}, located outside the experiment by |
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means of optical signals. The entire TIB and TID contains roughly 100 |
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means of optical signals. The entire TIB and TID contains a total of 110 |
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Control Rings. |
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\begin{description} |
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via a 26 poles flat cable. |
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To cope with possible CCU failures that would affect the entire ring, the |
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control ring features the so called {\it redundancy} by means of |
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a clever layout, shown in Fig.~\ref{fig:redundancy}, that exploits the |
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a {\it double path} layout, shown in Fig.~\ref{fig:redundancy}. |
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This design exploits the |
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two input/output replicas of the CCUs: each CCU is connected to the |
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two nearby CCUs through the primary circuit (``A'') and to the second |
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next CCUs through the secondary circuit (``B'') by which a failing CCU |
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\subsection{The Mother Cable} |
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The electrical connections between a group of modules served by the |
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same CCU are done by the {\it Mother Cable}~\cite{ref:mc}, a flexible |
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same CCU are done by the {\it Mother Cable}~\cite{ref:mc}, a |
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multi-layer kapton copper circuit. An example is shown in |
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Fig.~\ref{fig:fotomc}. The mother cable is mounted on the carbon fiber |
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support structure underneath the modules. |
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\begin{center} |
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\includegraphics[width=0.85\textwidth]{Figs/mothercable.pdf} |
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\end{center} |
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\caption{A mother cable mounted on a shell. In the two upper boxes, the detail of the CCU |
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installed on MC and the connectors at the edge of the MC.} |
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\caption{A TIB mother cable with module connectors and CCU (top); |
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details of the CCU and the connectors at the edge of the MC |
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(middle); three module assembled string (bottom).} |
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\label{fig:fotomc} |
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\end{figure} |
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